August 2022 Archives by date

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Starting: Mon Aug 1 18:49:47 PDT 2022
Ending: Wed Aug 31 14:04:40 PDT 2022
Messages: 1067

• [PATCH v8 00/31] Rust support   Miguel Ojeda
• [PATCH v8 27/31] Kbuild: add Rust support   Miguel Ojeda
• [PATCH v7 2/4] riscv: dts: fix the icicle's #pwm-cells   Uwe Kleine-König
• [PATCH v7 1/4] dt-bindings: pwm: fix microchip corePWM's pwm-cells   Uwe Kleine-König
• [PATCH v7 3/4] pwm: add microchip soft ip corePWM driver   Uwe Kleine-König
• [PATCH V5 0/6] RISC-V fixups to work with crash tool   Xianting Tian
• [PATCH V5 1/6] RISC-V: use __smp_processor_id() instead of smp_processor_id()   Xianting Tian
• [PATCH V5 2/6] RISC-V: Add arch_crash_save_vmcoreinfo support   Xianting Tian
• [PATCH V5 3/6] riscv: Add modules to virtual kernel memory layout dump   Xianting Tian
• [PATCH V5 4/6] RISC-V: Fixup getting correct current pc   Xianting Tian
• [PATCH V5 5/6] riscv: crash_core: Export kernel vm layout, phys_ram_base   Xianting Tian
• [PATCH V5 6/6] RISC-V: Fixup schedule out issue in machine_crash_shutdown()   Xianting Tian
• [PATCH v8 00/31] Rust support   Matthew Wilcox
• [PATCH v7 3/4] pwm: add microchip soft ip corePWM driver   Conor.Dooley at microchip.com
• [PATCH v8 00/31] Rust support   Miguel Ojeda
• [PATCH v8 00/31] Rust support   Christoph Hellwig
• [PATCH v8 00/31] Rust support   Matthew Wilcox
• [PATCH v8 00/31] Rust support   Miguel Ojeda
• [PATCH v8 00/31] Rust support   Miguel Ojeda
• [PATCH v8 00/31] Rust support   Miguel Ojeda
• [PATCH v4] dt-bindings: gpio: sifive: add gpio-line-names   Conor Dooley
• DT schema warnings on Risc-V virt machine   Rob Herring
• DT schema warnings on Risc-V virt machine   Conor Dooley
• [PATCH] dt-bindings: riscv: fix SiFive l2-cache's cache-sets   Conor Dooley
• DT schema warnings on Risc-V virt machine   Conor Dooley
• [PATCH v7 4/4] riscv: implement cache-management errata for T-Head SoCs   Palmer Dabbelt
• [PATCH] uapi: Fixup strace compile error   Palmer Dabbelt
• [PATCH] uapi: Fixup strace compile error   Guo Ren
• [PATCH] uapi: Fixup strace compile error   Guo Ren
• [PATCH] uapi: Fixup strace compile error   Guo Ren
• [PATCH V2] uapi: Fixup strace compile error   guoren at kernel.org
• [syzbot] riscv/fixes test error: lost connection to test machine   Dmitry Vyukov
• [PATCH v7 4/4] riscv: implement cache-management errata for T-Head SoCs   Arnd Bergmann
• [PATCH] dt-bindings: riscv: fix SiFive l2-cache's cache-sets   Krzysztof Kozlowski
• [Crash-utility][PATCH V2 0/9] Support RISCV64 arch and common commands   HAGIO KAZUHITO(萩尾　一仁)
• [Crash-utility][PATCH V2 0/9] Support RISCV64 arch and common commands   Xianting Tian
• Investment Opportunity   lists.infradead.org
• [PATCH 0/3] MPFS mailbox fixes   Conor Dooley
• [PATCH 1/3] dt-bindings: mailbox: fix the mpfs' reg property   Conor Dooley
• [PATCH 2/3] mailbox: mpfs: fix handling of the reg property   Conor Dooley
• [PATCH 3/3] mailbox: mpfs: account for mbox offsets while sending   Conor Dooley
• [PATCH 1/3] dt-bindings: mailbox: fix the mpfs' reg property   Conor.Dooley at microchip.com
• [PATCH] MAINTAINERS: add PolarFire SoC dt bindings   Conor Dooley
• [PATCH 0/5] QEMU: Fix RISC-V virt & spike machines' dtbs   Conor Dooley
• [PATCH 1/5] target/riscv: Ignore the S and U letters when formatting ISA strings   Conor Dooley
• [PATCH 2/5] hw/riscv: virt: fix uart node name   Conor Dooley
• [PATCH 3/5] hw/riscv: virt: Fix the plic's address cells   Conor Dooley
• [PATCH 4/5] hw/riscv: virt: fix syscon subnode paths   Conor Dooley
• [PATCH 5/5] hw/core: fix platform bus node name   Conor Dooley
• [PATCH v7 3/4] RISC-V: Prefer sstc extension if available   Atish Patra
• [PATCH 0/3] Fix dt-validate issues on qemu dtbdumps due to dt-bindings   Conor Dooley
• [PATCH 1/3] dt-bindings: timer: sifive,clint: add legacy riscv compatible   Conor Dooley
• [PATCH 2/3] dt-bindings: interrupt-controller: sifive,plic: add legacy riscv compatible   Conor Dooley
• [PATCH 3/3] dt-bindings: riscv: add new riscv,isa strings for emulators   Conor Dooley
• [PATCH v2] riscv: ensure cpu_ops_sbi is declared   Conor.Dooley at microchip.com
• [PATCH v5 00/13] Canaan devicetree fixes   Conor.Dooley at microchip.com
• DT schema warnings on Risc-V virt machine   Conor.Dooley at microchip.com
• [PATCH v7 3/4] pwm: add microchip soft ip corePWM driver   Uwe Kleine-König
• [PATCH v7 3/4] pwm: add microchip soft ip corePWM driver   Conor.Dooley at microchip.com
• [PATCH] spi: microchip-core: Simplify some error message   Christophe JAILLET
• [PATCH] spi: microchip-core: Simplify some error message   Conor.Dooley at microchip.com
• [GIT PULL] RISC-V Patches for the 5.20 Merge Window, Part 1   Palmer Dabbelt
• [GIT PULL] RISC-V Patches for the 5.20 Merge Window, Part 1   pr-tracker-bot at kernel.org
• [PATCH] riscv: compat: make __ARCH_WANT_COMPAT_FADVISE64_64 conditional   Randy Dunlap
• [PATCH] asm-generic: unistd.h: make 'compat_sys_fadvise64_64' conditional   Randy Dunlap
• [PATCH] riscv: compat: make __ARCH_WANT_COMPAT_FADVISE64_64 conditional   Arnd Bergmann
• [PATCH] asm-generic: unistd.h: make 'compat_sys_fadvise64_64' conditional   Arnd Bergmann
• [PATCH v2] kernel/sys_ni: add compat entry for fadvise64_64   Randy Dunlap
• [PATCH] asm-generic: unistd.h: make 'compat_sys_fadvise64_64' conditional   Randy Dunlap
• [PATCH 1/5] target/riscv: Ignore the S and U letters when formatting ISA strings   Alistair Francis
• [PATCH 3/5] hw/riscv: virt: Fix the plic's address cells   Alistair Francis
• [PATCH 2/5] hw/riscv: virt: fix uart node name   Alistair Francis
• [PATCH 4/5] hw/riscv: virt: fix syscon subnode paths   Alistair Francis
• [PATCH 5/5] hw/core: fix platform bus node name   Alistair Francis
• [PATCH 1/5] target/riscv: Ignore the S and U letters when formatting ISA strings   Conor.Dooley at microchip.com
• [PATCH v2] kernel/sys_ni: add compat entry for fadvise64_64   Arnd Bergmann
• [PATCH 1/3] dt-bindings: mailbox: fix the mpfs' reg property   Krzysztof Kozlowski
• [PATCH V9 00/15] arch: Add qspinlock support and atomic cleanup   guoren at kernel.org
• [PATCH V9 01/15] asm-generic: ticket-lock: Remove unnecessary atomic_read   guoren at kernel.org
• [PATCH V9 02/15] asm-generic: ticket-lock: Use the same struct definitions with qspinlock   guoren at kernel.org
• [PATCH V9 03/15] asm-generic: ticket-lock: Move into ticket_spinlock.h   guoren at kernel.org
• [PATCH V9 04/15] asm-generic: ticket-lock: Keep ticket-lock the same semantic with qspinlock   guoren at kernel.org
• [PATCH V9 05/15] asm-generic: spinlock: Add queued spinlock support in common header   guoren at kernel.org
• [PATCH V9 06/15] riscv: atomic: Clean up unnecessary acquire and release definitions   guoren at kernel.org
• [PATCH V9 07/15] riscv: cmpxchg: Remove xchg32 and xchg64   guoren at kernel.org
• [PATCH V9 08/15] riscv: cmpxchg: Forbid arch_cmpxchg64 for 32-bit   guoren at kernel.org
• [PATCH V9 09/15] riscv: cmpxchg: Optimize cmpxchg64   guoren at kernel.org
• [PATCH V9 10/15] riscv: Enable ARCH_INLINE_READ*/WRITE*/SPIN*   guoren at kernel.org
• [PATCH V9 11/15] riscv: Add qspinlock support   guoren at kernel.org
• [PATCH V9 12/15] riscv: Add combo spinlock support   guoren at kernel.org
• [PATCH V9 13/15] openrisc: cmpxchg: Cleanup unnecessary codes   guoren at kernel.org
• [PATCH V9 14/15] openrisc: Move from ticket-lock to qspinlock   guoren at kernel.org
• [PATCH V9 15/15] csky: spinlock: Use the generic header files   guoren at kernel.org
• [PATCH V9 00/15] arch: Add qspinlock support and atomic cleanup   Guo Ren
• [GIT PULL] RISC-V Patches for the 5.20 Merge Window, Part 1   Ben Dooks
• [PATCH] MAINTAINERS: add PolarFire SoC dt bindings   Marc Kleine-Budde
• [RFC PATCH 0/4] riscv: Add basic percpu operations   guoren at kernel.org
• [RFC PATCH 1/4] vmstat: percpu: Rename HAVE_CMPXCHG_LOCAL to HAVE_CMPXCHG_PERCPU_BYTE   guoren at kernel.org
• [RFC PATCH 2/4] arm64: percpu: Use generic PERCPU_RW_OPS   guoren at kernel.org
• [RFC PATCH 3/4] riscv: percpu: Implement this_cpu operations   guoren at kernel.org
• [RFC PATCH 4/4] riscv: cmpxchg: Remove unused cmpxchg(64)_local   guoren at kernel.org
• [PATCH] asm-generic: unistd.h: make 'compat_sys_fadvise64_64' conditional   Arnd Bergmann
• [PATCH v7 3/4] RISC-V: Prefer sstc extension if available   Guo Ren
• [RFC PATCH 1/4] vmstat: percpu: Rename HAVE_CMPXCHG_LOCAL to HAVE_CMPXCHG_PERCPU_BYTE   Christoph Lameter
• [GIT PULL] RISC-V Patches for the 5.20 Merge Window, Part 1   Jason A. Donenfeld
• [GIT PULL] RISC-V Patches for the 5.20 Merge Window, Part 1   Jason A. Donenfeld
• [PATCH 1/5] target/riscv: Ignore the S and U letters when formatting ISA strings   Tsukasa OI
• [PATCH 1/5] target/riscv: Ignore the S and U letters when formatting ISA strings   Conor.Dooley at microchip.com
• [PATCH 1/5] target/riscv: Ignore the S and U letters when formatting ISA strings   Alistair Francis
• [PATCH 1/5] target/riscv: Ignore the S and U letters when formatting ISA strings   Conor.Dooley at microchip.com
• [PATCH v2 0/4] QEMU: Fix RISC-V virt & spike machines' dtbs   Conor Dooley
• [PATCH v2 1/4] hw/riscv: virt: fix uart node name   Conor Dooley
• [PATCH v2 2/4] hw/riscv: virt: Fix the plic's address cells   Conor Dooley
• [PATCH v2 3/4] hw/riscv: virt: fix syscon subnode paths   Conor Dooley
• [PATCH v2 4/4] hw/core: fix platform bus node name   Conor Dooley
• [PATCH v2 3/4] hw/riscv: virt: fix syscon subnode paths   Jessica Clarke
• [PATCH 0/3] Fix dt-validate issues on qemu dtbdumps due to dt-bindings   Jessica Clarke
• [PATCH 0/3] Fix dt-validate issues on qemu dtbdumps due to dt-bindings   Conor.Dooley at microchip.com
• [PATCH v2 3/4] hw/riscv: virt: fix syscon subnode paths   Conor.Dooley at microchip.com
• [PATCH v2 3/4] hw/riscv: virt: fix syscon subnode paths   Rob Herring
• [RFC PATCH 1/4] vmstat: percpu: Rename HAVE_CMPXCHG_LOCAL to HAVE_CMPXCHG_PERCPU_BYTE   Guo Ren
• [PATCH v2 3/4] hw/riscv: virt: fix syscon subnode paths   Conor.Dooley at microchip.com
• [PATCH V5 0/6] RISC-V fixups to work with crash tool   Xianting Tian
• [PATCH V4 5/5] riscv: atomic: Optimize LRSC-pairs atomic ops with .aqrl annotation   Guo Ren
• [PATCH -next] riscv: lib: uaccess: fix CSR_STATUS SR_SUM bit   chenlifu
• [PATCH 0/3] Fix dt-validate issues on qemu dtbdumps due to dt-bindings   Rob Herring
• [PATCH 1/3] dt-bindings: timer: sifive,clint: add legacy riscv compatible   Rob Herring
• [PATCH] wireguard: selftests: set CONFIG_NONPORTABLE on riscv32   Jason A. Donenfeld
• [PATCH v7 3/4] RISC-V: Prefer sstc extension if available   Atish Patra
• [PATCH 0/3] Fix dt-validate issues on qemu dtbdumps due to dt-bindings   Conor.Dooley at microchip.com
• [PATCH 1/3] dt-bindings: timer: sifive,clint: add legacy riscv compatible   Conor.Dooley at microchip.com
• [PATCH 0/3] Fix dt-validate issues on qemu dtbdumps due to dt-bindings   Conor.Dooley at microchip.com
• [PATCH V5 1/6] RISC-V: use __smp_processor_id() instead of smp_processor_id()   Conor.Dooley at microchip.com
• [PATCH V5 4/6] RISC-V: Fixup getting correct current pc   Conor.Dooley at microchip.com
• [PATCH V5 4/6] RISC-V: Fixup getting correct current pc   Conor.Dooley at microchip.com
• [PATCH V5 5/6] riscv: crash_core: Export kernel vm layout, phys_ram_base   Conor.Dooley at microchip.com
• [PATCH V5 6/6] RISC-V: Fixup schedule out issue in machine_crash_shutdown()   Conor.Dooley at microchip.com
• [PATCH V5 0/6] RISC-V fixups to work with crash tool   Conor.Dooley at microchip.com
• [PATCH v2 00/12] PolarFire SoC reset controller & clock cleanups   Conor.Dooley at microchip.com
• In der Stadt Aalen wurden mehr als 875 Menschen Millionare   WordPress
• [PATCH] RISC-V: defconfig: Remove CONFIG_SECURITY   Palmer Dabbelt
• [PATCH v2 0/2] perf: RISC-V: fix access beyond allocated array   Sergey Matyukevich
• [PATCH] riscv: dts: microchip: add qspi compatible fallback   Conor Dooley
• [PATCH v2 00/12] PolarFire SoC reset controller & clock cleanups   Daire.McNamara at microchip.com
• [PATCH V5 5/6] riscv: crash_core: Export kernel vm layout, phys_ram_base   Xianting Tian
• [PATCH] riscv: dts: microchip: add qspi compatible fallback   Krzysztof Kozlowski
• [RESEND/PULL PATCH 0/2] MAINTAINERS updates for PolarFire SoC   Conor Dooley
• [RESEND PATCH 1/2] MAINTAINERS: add PolarFire SoC dt bindings   Conor Dooley
• [RESEND PATCH 2/2] MAINTAINERS: add the Polarfire SoC's i2c driver   Conor Dooley
• [PATCH v5] perf arch events: riscv sbi firmware std event files   Mayuresh Chitale
• [RESEND PATCH 1/2] MAINTAINERS: add PolarFire SoC dt bindings   Uwe Kleine-König
• [PATCH v3 0/4] QEMU: Fix RISC-V virt & spike machines' dtbs   Conor Dooley
• [PATCH v3 1/4] hw/riscv: virt: fix uart node name   Conor Dooley
• [PATCH v3 2/4] hw/riscv: virt: fix the plic's address cells   Conor Dooley
• [PATCH v3 3/4] hw/riscv: virt: fix syscon subnode paths   Conor Dooley
• [PATCH v3 4/4] hw/core: fix platform bus node name   Conor Dooley
• [PATCH v2 00/12] PolarFire SoC reset controller & clock cleanups   Nathan Chancellor
• [PATCH v2 00/12] PolarFire SoC reset controller & clock cleanups   Conor.Dooley at microchip.com
• [PATCH v2 00/12] PolarFire SoC reset controller & clock cleanups   Nathan Chancellor
• [PATCH v2 00/12] PolarFire SoC reset controller & clock cleanups   Conor.Dooley at microchip.com
• [PATCH -next] riscv: lib: uaccess: fix CSR_STATUS SR_SUM bit   Palmer Dabbelt
• [PATCH v5 00/13] Canaan devicetree fixes   Palmer Dabbelt
• [PATCH V5 0/6] RISC-V fixups to work with crash tool   Xianting Tian
• [PATCH V5 5/6] riscv: crash_core: Export kernel vm layout, phys_ram_base   Bagas Sanjaya
• [PATCH V5 5/6] riscv: crash_core: Export kernel vm layout, phys_ram_base   Xianting Tian
• [PATCH v7 0/4] riscv: implement Zicbom-based CMO instructions + the t-head variant   Palmer Dabbelt
• [PATCH v2] RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo output   Anup Patel
• [PATCH v5 00/13] Canaan devicetree fixes   Conor.Dooley at microchip.com
• [PATCH] MAINTAINERS: rectify entry for RISC-V/MICROCHIP POLARFIRE SOC SUPPORT   Lukas Bulwahn
• [PATCH] MAINTAINERS: rectify entry for RISC-V/MICROCHIP POLARFIRE SOC SUPPORT   Conor.Dooley at microchip.com
• [PATCH] MAINTAINERS: rectify entry for RISC-V/MICROCHIP POLARFIRE SOC SUPPORT   Lukas Bulwahn
• [PATCH V6 0/6] RISC-V fixups to work with crash tool   Xianting Tian
• [PATCH V6 1/6] RISC-V: kexec: Fixup use of smp_processor_id() in preemptible context   Xianting Tian
• [PATCH V6 2/6] RISC-V: Fixup get incorrect user mode PC for kernel mode regs   Xianting Tian
• [PATCH V6 3/6] RISC-V: Fixup schedule out issue in machine_crash_shutdown()   Xianting Tian
• [PATCH V6 4/6] RISC-V: Add modules to virtual kernel memory layout dump   Xianting Tian
• [PATCH V6 5/6] RISC-V: Add arch_crash_save_vmcoreinfo support   Xianting Tian
• [PATCH V6 6/6] Documentation: kdump: describe VMCOREINFO export for RISCV64   Xianting Tian
• [PATCH] MAINTAINERS: rectify entry for RISC-V/MICROCHIP POLARFIRE SOC SUPPORT   Conor.Dooley at microchip.com
• [PATCH v5] perf arch events: riscv sbi firmware std event files   Nikita Shubin
• [PATCH] MAINTAINERS: rectify entry for RISC-V/MICROCHIP POLARFIRE SOC SUPPORT   Conor.Dooley at microchip.com
• [PATCH] MAINTAINERS: rectify entry for RISC-V/MICROCHIP POLARFIRE SOC SUPPORT   Wolfram Sang
• [PATCH v2 00/12] PolarFire SoC reset controller & clock cleanups   Conor.Dooley at microchip.com
• [PATCH V6 6/6] Documentation: kdump: describe VMCOREINFO export for RISCV64   Bagas Sanjaya
• [PATCH v4] arch/riscv: add Zihintpause support   Palmer Dabbelt
• [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch   Geert Uytterhoeven
• [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK   Geert Uytterhoeven
• [PATCH V6 0/6] RISC-V fixups to work with crash tool   Conor.Dooley at microchip.com
• [PATCH] RISC-V: use __smp_processor_id() instead of smp_processor_id()   Palmer Dabbelt
• [PATCH] riscv: traps_misaligned: do not duplicate stringify   Palmer Dabbelt
• [PATCH] RISC-V: use __smp_processor_id() instead of smp_processor_id()   Palmer Dabbelt
• [PATCH V6 0/6] RISC-V fixups to work with crash tool   Palmer Dabbelt
• [PATCH] irqchip/sifive-plic: Make struct irq_chip const   Palmer Dabbelt
• [PATCH v2 1/2] riscv/purgatory: hard-code obj-y in Makefile   Palmer Dabbelt
• [PATCH] riscv/kprobes: allocate detour buffer from module area   Palmer Dabbelt
• [PATCH] irqchip/sifive-plic: Make struct irq_chip const   Marc Zyngier
• [PATCH] dt-bindings: mmc: cdns: add card-detect-delay property   Conor Dooley
• [PATCH] riscv: dts: microchip: remove ti,fifo-depth property   Conor Dooley
• [PATCH 0/4] Fix RISC-V/PCI dt-schema issues with dt-schema v2022.08   Conor Dooley
• [PATCH 1/4] dt-bindings: PCI: fu740-pci: fix missing clock-names   Conor Dooley
• [PATCH 2/4] dt-bindings: PCI: microchip,pcie-host: fix missing clocks properties   Conor Dooley
• [PATCH 3/4] dt-bindings: PCI: microchip,pcie-host: fix incorrect child node name   Conor Dooley
• [PATCH 4/4] dt-bindings: PCI: microchip,pcie-host: fix missing address translation property   Conor Dooley
• [PATCH] riscv: dts: microchip: remove ti,fifo-depth property   Conor.Dooley at microchip.com
• [PATCH v1 0/4] Add HiFive Unmatched LEDs   Palmer Dabbelt
• [PATCH v2] riscv: dts: starfive: correct number of external interrupts   Palmer Dabbelt
• [PATCH] RISC-V: cpu_ops_spinwait.c should include head.h   Palmer Dabbelt
• [PATCH] RISC-V: cpu_ops_spinwait.c should include head.h   Palmer Dabbelt
• [PATCH] riscv/vdso: fix missing vdso_data declaration   Palmer Dabbelt
• [PATCH] dt-bindings: riscv: fix SiFive l2-cache's cache-sets   Palmer Dabbelt
• [PATCH] riscv/vdso: fix missing vdso_data declaration   Conor.Dooley at microchip.com
• [PATCH v4] riscv:uprobe fix SR_SPIE set/clear handling   Palmer Dabbelt
• [PATCH v7 0/4] Add Sstc extension support   Palmer Dabbelt
• [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch   Lad, Prabhakar
• Apply f2928e224d85e7cc139009ab17cefdfec2df5d11 to 5.15 and 5.10?   Nathan Chancellor
• [v3 0/5] Miscallenous improvement & fixes for the PMU driver   Palmer Dabbelt
• Apply f2928e224d85e7cc139009ab17cefdfec2df5d11 to 5.15 and 5.10?   Ron Economos
• [PATCH V6 0/6] RISC-V fixups to work with crash tool   Xianting Tian
• [PATCH v7 0/4] Add Sstc extension support   Anup Patel
• [RFC PATCH v3 0/2] Risc-V Svinval support   Mayuresh Chitale
• [RFC PATCH v3 1/2] riscv: enum for svinval extension   Mayuresh Chitale
• [RFC PATCH v3 2/2] riscv: mm: use svinval instructions instead of sfence.vma   Mayuresh Chitale
• [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK   Krzysztof Kozlowski
• [PATCH v4] arch/riscv: add Zihintpause support   Conor.Dooley at microchip.com
• [PATCH v4] arch/riscv: add Zihintpause support   Conor.Dooley at microchip.com
• [PATCH 1/4] dt-bindings: PCI: fu740-pci: fix missing clock-names   Krzysztof Kozlowski
• [PATCH 2/4] dt-bindings: PCI: microchip,pcie-host: fix missing clocks properties   Krzysztof Kozlowski
• [PATCH 3/4] dt-bindings: PCI: microchip,pcie-host: fix incorrect child node name   Krzysztof Kozlowski
• [PATCH 4/4] dt-bindings: PCI: microchip,pcie-host: fix missing address translation property   Krzysztof Kozlowski
• [PATCH 3/4] dt-bindings: PCI: microchip,pcie-host: fix incorrect child node name   Conor.Dooley at microchip.com
• [PATCH 1/4] dt-bindings: PCI: fu740-pci: fix missing clock-names   Conor.Dooley at microchip.com
• [PATCH 2/4] dt-bindings: PCI: microchip,pcie-host: fix missing clocks properties   Krzysztof Kozlowski
• [PATCH 2/4] dt-bindings: PCI: microchip,pcie-host: fix missing clocks properties   Conor.Dooley at microchip.com
• [PATCH 4/4] dt-bindings: PCI: microchip,pcie-host: fix missing address translation property   Conor.Dooley at microchip.com
• [PATCH -next] riscv: extable: add new extable type EX_TYPE_KACCESS_ERR_ZERO support   Tong Tiangen
• [PATCH -next] riscv: extable: add new extable type EX_TYPE_KACCESS_ERR_ZERO support   Conor.Dooley at microchip.com
• [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK   Lad, Prabhakar
• [PATCH 3/4] dt-bindings: PCI: microchip,pcie-host: fix incorrect child node name   Krzysztof Kozlowski
• [PATCH -next] riscv: extable: add new extable type EX_TYPE_KACCESS_ERR_ZERO support   Tong Tiangen
• [PATCH] perf: riscv: fix broken build due to struct redefinition   Conor Dooley
• [PATCH] perf: riscv: fix broken build due to struct redefinition   Jessica Clarke
• [PATCH] perf: riscv: fix broken build due to struct redefinition   Conor.Dooley at microchip.com
• [PATCH] RISC-V: Don't truncate a hartid in the cbom-block-size mismatch warning   Palmer Dabbelt
• [PATCH] perf: riscv legacy: fix kerneldoc comment warning   Conor Dooley
• [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK   Palmer Dabbelt
• [PATCH] RISC-V: Don't truncate a hartid in the cbom-block-size mismatch warning   Anup Patel
• [PATCH] RISC-V: Don't truncate a hartid in the cbom-block-size mismatch warning   Conor.Dooley at microchip.com
• [PATCH] dt-bindings: mmc: cdns: add card-detect-delay property   Rob Herring
• Apply f2928e224d85e7cc139009ab17cefdfec2df5d11 to 5.15 and 5.10?   Greg Kroah-Hartman
• [PATCH v2] RISC-V: Clean up the Zicbom block size probing   Palmer Dabbelt
• [PATCH] dt-bindings: mmc: cdns: add card-detect-delay property   Conor.Dooley at microchip.com
• [PATCH] wireguard: selftests: set CONFIG_NONPORTABLE on riscv32   Palmer Dabbelt
• [PATCH v7 0/4] Add Sstc extension support   Palmer Dabbelt
• [PATCH] RISC-V: Don't truncate a hartid in the cbom-block-size mismatch warning   Palmer Dabbelt
• [PATCH v4] dt-bindings: gpio: sifive: add gpio-line-names   Palmer Dabbelt
• [GIT PULL] RISC-V Patches for the 5.20 Merge Window, Part 1   Palmer Dabbelt
• randconfig linker errors   Conor.Dooley at microchip.com
• [PATCH] dt-bindings: mmc: cdns: add card-detect-delay property   Rob Herring
• Apply f2928e224d85e7cc139009ab17cefdfec2df5d11 to 5.15 and 5.10?   Palmer Dabbelt
• [PATCH] dt-bindings: mmc: cdns: add card-detect-delay property   Conor.Dooley at microchip.com
• Apply f2928e224d85e7cc139009ab17cefdfec2df5d11 to 5.15 and 5.10?   Conor.Dooley at microchip.com
• [PATCH v2] RISC-V: Clean up the Zicbom block size probing   Conor.Dooley at microchip.com
• [PATCH v2] RISC-V: Clean up the Zicbom block size probing   Atish Patra
• [PATCH] dt-bindings: mmc: cdns: add card-detect-delay property   Conor.Dooley at microchip.com
• [PATCH v5] perf arch events: riscv sbi firmware std event files   Arnaldo Carvalho de Melo
• [PATCH 1/1] riscv: enable CD-ROM file systems in defconfig   Heinrich Schuchardt
• [PATCH] RISC-V: defconfig: Remove CONFIG_SECURITY   Palmer Dabbelt
• [PATCH] perf: riscv: fix broken build due to struct redefinition   Palmer Dabbelt
• [PATCH] perf: riscv: fix broken build due to struct redefinition   Conor.Dooley at microchip.com
• [PATCH v2] RISC-V: Clean up the Zicbom block size probing   Palmer Dabbelt
• [GIT PULL] RISC-V Patches for the 5.20 Merge Window, Part 2   Palmer Dabbelt
• [GIT PULL] RISC-V Patches for the 5.20 Merge Window, Part 2   pr-tracker-bot at kernel.org
• [Crash-utility][PATCH V3 0/9] Support RISCV64 arch and common commands   Xianting Tian
• [Crash-utility][PATCH V3 1/9] Add RISCV64 framework code support   Xianting Tian
• [Crash-utility][PATCH V3 2/9] RISCV64: Make crash tool enter command line and support some commands   Xianting Tian
• [Crash-utility][PATCH V3 3/9] RISCV64: Add 'dis' command support   Xianting Tian
• [Crash-utility][PATCH V3 4/9] RISCV64: Add 'irq' command support   Xianting Tian
• [Crash-utility][PATCH V3 5/9] RISCV64: Add 'bt' command support   Xianting Tian
• [Crash-utility][PATCH V3 6/9] RISCV64: Add 'help -r' command support   Xianting Tian
• [Crash-utility][PATCH V3 7/9] RISCV64: Add 'help -m/M' command support   Xianting Tian
• [Crash-utility][PATCH V3 8/9] RISCV64: Add 'mach' command support   Xianting Tian
• [Crash-utility][PATCH V3 9/9] RISCV64: Add the implementation of symbol verify   Xianting Tian
• [PATCH 1/1] riscv: enable Docker requirements in defconfig   Guenter Roeck
• [PATCH v2] kernel/sys_ni: add compat entry for fadvise64_64   Conor.Dooley at microchip.com
• randconfig linker errors   Conor.Dooley at microchip.com
• [PATCH v2] kernel/sys_ni: add compat entry for fadvise64_64   Randy Dunlap
• [PATCH] checkpatch: Add kmap and kmap_atomic to the deprecated list   ira.weiny at intel.com
• [PATCH v6 0/2] use static key to optimize pgtable_l4_enabled   Jisheng Zhang
• [PATCH] checkpatch: Add kmap and kmap_atomic to the deprecated list   Chaitanya Kulkarni
• [PATCH v2 00/12] PolarFire SoC reset controller & clock cleanups   Conor.Dooley at microchip.com
• [PATCH 2/4] dt-bindings: PCI: microchip,pcie-host: fix missing clocks properties   Conor.Dooley at microchip.com
• [PATCH 0/4] misc warning cleanup in arch/risc-v   Conor Dooley
• [PATCH 1/4] riscv: kvm: vcpu_timer: fix unused variable warnings   Conor Dooley
• [PATCH 2/4] riscv: kvm: move extern sbi_ext declarations to a header   Conor Dooley
• [PATCH 3/4] riscv: signal: fix missing prototype warning   Conor Dooley
• [PATCH 4/4] riscv: traps: add missing prototype   Conor Dooley
• [PATCH] riscv/vdso: fix missing vdso_data declaration   Conor.Dooley at microchip.com
• [PATCH AUTOSEL 5.19 08/48] riscv: dts: microchip: Add mpfs' topology information   Sasha Levin
• [PATCH AUTOSEL 5.19 16/48] riscv: dts: sifive: Add fu540 topology information   Sasha Levin
• [PATCH AUTOSEL 5.19 17/48] riscv: dts: sifive: Add fu740 topology information   Sasha Levin
• [PATCH AUTOSEL 5.19 18/48] riscv: dts: canaan: Add k210 topology information   Sasha Levin
• [PATCH AUTOSEL 5.19 20/48] riscv: mmap with PROT_WRITE but no PROT_READ is invalid   Sasha Levin
• [PATCH AUTOSEL 5.19 21/48] RISC-V: Add fast call path of crash_kexec()   Sasha Levin
• [PATCH AUTOSEL 5.18 07/39] riscv: dts: microchip: Add mpfs' topology information   Sasha Levin
• [PATCH AUTOSEL 5.18 11/39] riscv: dts: sifive: Add fu540 topology information   Sasha Levin
• [PATCH AUTOSEL 5.18 12/39] riscv: dts: sifive: Add fu740 topology information   Sasha Levin
• [PATCH AUTOSEL 5.18 13/39] riscv: dts: canaan: Add k210 topology information   Sasha Levin
• [PATCH AUTOSEL 5.18 14/39] riscv: mmap with PROT_WRITE but no PROT_READ is invalid   Sasha Levin
• [PATCH AUTOSEL 5.18 15/39] RISC-V: Add fast call path of crash_kexec()   Sasha Levin
• [PATCH AUTOSEL 5.15 09/28] riscv: dts: sifive: Add fu540 topology information   Sasha Levin
• [PATCH AUTOSEL 5.15 10/28] riscv: dts: sifive: Add fu740 topology information   Sasha Levin
• [PATCH AUTOSEL 5.15 11/28] riscv: dts: canaan: Add k210 topology information   Sasha Levin
• [PATCH AUTOSEL 5.15 12/28] riscv: mmap with PROT_WRITE but no PROT_READ is invalid   Sasha Levin
• [PATCH AUTOSEL 5.15 13/28] RISC-V: Add fast call path of crash_kexec()   Sasha Levin
• [PATCH AUTOSEL 5.10 06/19] riscv: dts: sifive: Add fu540 topology information   Sasha Levin
• [PATCH AUTOSEL 5.10 07/19] riscv: mmap with PROT_WRITE but no PROT_READ is invalid   Sasha Levin
• [PATCH AUTOSEL 5.10 08/19] RISC-V: Add fast call path of crash_kexec()   Sasha Levin
• [PATCH AUTOSEL 5.4 05/16] riscv: dts: sifive: Add fu540 topology information   Sasha Levin
• [PATCH AUTOSEL 5.4 06/16] riscv: mmap with PROT_WRITE but no PROT_READ is invalid   Sasha Levin
• [PATCH AUTOSEL 5.4 07/16] RISC-V: Add fast call path of crash_kexec()   Sasha Levin
• [PATCH AUTOSEL 4.19 05/14] riscv: mmap with PROT_WRITE but no PROT_READ is invalid   Sasha Levin
• [PATCH AUTOSEL 4.19 06/14] RISC-V: Add fast call path of crash_kexec()   Sasha Levin
• [PATCH AUTOSEL 5.19 08/48] riscv: dts: microchip: Add mpfs' topology information   Conor.Dooley at microchip.com
• [PATCH v3 3/4] hw/riscv: virt: fix syscon subnode paths   Alistair Francis
• [PATCH -next v2 0/2]riscv: some refactorings realted to uaccess and extable   Tong Tiangen
• [PATCH -next v2 1/2] riscv: uaccess: rename __get/put_user_nocheck to __get/put_mem_nocheck   Tong Tiangen
• [PATCH -next v2 2/2] riscv: extable: add new extable type EX_TYPE_KACCESS_ERR_ZERO support   Tong Tiangen
• [PATCH 00/12] riscv: Allwinner D1 platform support   Samuel Holland
• [PATCH 01/12] MAINTAINERS: Match the sun20i family of Allwinner SoCs   Samuel Holland
• [PATCH 02/12] dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles   Samuel Holland
• [PATCH 03/12] dt-bindings: vendor-prefixes: Add Allwinner D1 board vendors   Samuel Holland
• [PATCH 04/12] dt-bindings: riscv: Add Allwinner D1 board compatibles   Samuel Holland
• [PATCH 05/12] riscv: Add the Allwinner SoC family Kconfig option   Samuel Holland
• [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree   Samuel Holland
• [PATCH 07/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree   Samuel Holland
• [PATCH 08/12] riscv: dts: allwinner: Add Sipeed Lichee RV devicetrees   Samuel Holland
• [PATCH 09/12] riscv: dts: allwinner: Add MangoPi MQ Pro devicetree   Samuel Holland
• [PATCH 10/12] riscv: dts: allwinner: Add Dongshan Nezha STU devicetree   Samuel Holland
• [PATCH 11/12] riscv: dts: allwinner: Add ClockworkPi and DevTerm devicetrees   Samuel Holland
• [PATCH 12/12] riscv: defconfig: Enable the Allwinner D1 platform and drivers   Samuel Holland
• [PATCH v4 0/1] Add Polarfire SoC GPIO support   lewis.hanly at microchip.com
• [PATCH v4 1/1] gpio: mpfs: add polarfire soc gpio support   lewis.hanly at microchip.com
• [PATCH 00/12] riscv: Allwinner D1 platform support   Conor.Dooley at microchip.com
• [PATCH v5 0/1] Add Polarfire SoC GPIO support   lewis.hanly at microchip.com
• [PATCH v5 1/1] gpio: mpfs: add polarfire soc gpio support   lewis.hanly at microchip.com
• [PATCH v5 1/1] gpio: mpfs: add polarfire soc gpio support   Christophe JAILLET
• [PATCH] riscv : select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY   sugarfillet at yeah.net
• [PATCH v5 1/1] gpio: mpfs: add polarfire soc gpio support   kernel test robot
• [PATCH v5 1/1] gpio: mpfs: add polarfire soc gpio support   Lewis.Hanly at microchip.com
• [PATCH v6 0/1] Add Polarfire SoC GPIO support   lewis.hanly at microchip.com
• [PATCH v6 1/1] gpio: mpfs: add polarfire soc gpio support   lewis.hanly at microchip.com
• [PATCH v6 0/1] Add Polarfire SoC GPIO support   Marc Zyngier
• [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree   Andre Przywara
• [PATCH v6 0/3] RISC-V: Create unique identification for SoC PMU   Nikita Shubin
• [PATCH v6 1/3] perf tools riscv: Add support for get_cpuid_str function   Nikita Shubin
• [PATCH v6 2/3] perf arch events: riscv sbi firmware std event files   Nikita Shubin
• [PATCH v6 3/3] perf vendor events riscv: add Sifive U74 JSON file   Nikita Shubin
• [PATCH v5] perf arch events: riscv sbi firmware std event files   Nikita Shubin
• [PATCH v2 0/8] Add support for Renesas RZ/Five SoC   Lad Prabhakar
• [PATCH v2 1/8] dt-bindings: riscv: Sort the CPU core list alphabetically   Lad Prabhakar
• [PATCH v2 2/8] dt-bindings: riscv: Add Andes AX45MP core to the list   Lad Prabhakar
• [PATCH v2 3/8] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC   Lad Prabhakar
• [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option   Lad Prabhakar
• [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC   Lad Prabhakar
• [PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK   Lad Prabhakar
• [PATCH v2 7/8] MAINTAINERS: Add entry for Renesas RISC-V architecture   Lad Prabhakar
• [PATCH v2 8/8] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC   Lad Prabhakar
• [PATCH v2] RISC-V: Clean up the Zicbom block size probing   Nathan Chancellor
• [PATCH] spi: microchip-core: Simplify some error message   Mark Brown
• [PATCH v6 1/1] gpio: mpfs: add polarfire soc gpio support   Conor.Dooley at microchip.com
• [PATCH v2 0/2] dt-bindings: sifive: fix dt-schema errors   Atul Khare
• Apply f2928e224d85e7cc139009ab17cefdfec2df5d11 to 5.15 and 5.10?   Nathan Chancellor
• [PATCH v2 0/2] dt-bindings: sifive: fix dt-schema errors   Conor.Dooley at microchip.com
• [PATCH 05/12] riscv: Add the Allwinner SoC family Kconfig option   Conor.Dooley at microchip.com
• [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree   Conor.Dooley at microchip.com
• [PATCH 01/12] MAINTAINERS: Match the sun20i family of Allwinner SoCs   Heiko Stübner
• [PATCH 02/12] dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles   Heiko Stübner
• [PATCH 03/12] dt-bindings: vendor-prefixes: Add Allwinner D1 board vendors   Heiko Stübner
• [PATCH 00/12] riscv: Allwinner D1 platform support   Conor.Dooley at microchip.com
• [PATCH 05/12] riscv: Add the Allwinner SoC family Kconfig option   Heiko Stübner
• [PATCH v2] RISC-V: Clean up the Zicbom block size probing   Jessica Clarke
• [PATCH 07/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree   Conor.Dooley at microchip.com
• [PATCH v2] RISC-V: Clean up the Zicbom block size probing   Nathan Chancellor
• [PATCH 07/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree   Conor.Dooley at microchip.com
• [PATCH v2 8/8] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC   Conor.Dooley at microchip.com
• [PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK   Conor.Dooley at microchip.com
• [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option   Conor.Dooley at microchip.com
• [PATCH v2 1/8] dt-bindings: riscv: Sort the CPU core list alphabetically   Conor.Dooley at microchip.com
• [PATCH v2 3/8] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC   Conor.Dooley at microchip.com
• [PATCH 0/3] Fix dt-validate issues on qemu dtbdumps due to dt-bindings   Conor.Dooley at microchip.com
• [PATCH v2 3/8] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC   Lad, Prabhakar
• [PATCH v2 3/8] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC   Conor.Dooley at microchip.com
• [PATCH v2 8/8] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC   Lad, Prabhakar
• [PATCH v2 8/8] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC   Conor.Dooley at microchip.com
• [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option   Lad, Prabhakar
• [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option   Conor.Dooley at microchip.com
• [PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK   Lad, Prabhakar
• [PATCH] riscv: dts: microchip: add qspi compatible fallback   Conor Dooley
• [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option   Lad, Prabhakar
• [GIT PULL] Fix RISC-V's arch-topology reporting   Conor.Dooley at microchip.com
• [PATCH 0/2] riscv: kexec: Support crash_save percpu and machine_kexec_mask_interrupts   guoren at kernel.org
• [PATCH 1/2] riscv: kexec: EOI active and mask all interrupts in kexec crash path   guoren at kernel.org
• [PATCH 2/2] riscv: kexec: Implement crash_smp_send_stop with percpu crash_save_cpu   guoren at kernel.org
• [PATCH 00/12] riscv: Allwinner D1 platform support   Samuel Holland
• [PATCH 00/12] riscv: Allwinner D1 platform support   Conor.Dooley at microchip.com
• [PATCH 0/2] riscv: kexec: Support crash_save percpu and machine_kexec_mask_interrupts   Conor.Dooley at microchip.com
• [PATCH 2/4] dt-bindings: PCI: microchip,pcie-host: fix missing clocks properties   Krzysztof Kozlowski
• [PATCH 04/12] dt-bindings: riscv: Add Allwinner D1 board compatibles   Krzysztof Kozlowski
• [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree   Krzysztof Kozlowski
• [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree   Jernej Škrabec
• [PATCH v2 3/8] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC   Krzysztof Kozlowski
• [PATCH 07/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree   Heiko Stübner
• [PATCH 04/12] dt-bindings: riscv: Add Allwinner D1 board compatibles   Heiko Stübner
• [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree   Heiko Stübner
• [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree   Heiko Stübner
• [GIT PULL] Fix RISC-V's arch-topology reporting   Sudeep Holla
• [PATCH 04/12] dt-bindings: riscv: Add Allwinner D1 board compatibles   Heiko Stübner
• [PATCH 05/12] riscv: Add the Allwinner SoC family Kconfig option   Heiko Stübner
• [PATCH 05/12] riscv: Add the Allwinner SoC family Kconfig option   Conor.Dooley at microchip.com
• [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree   Jernej Škrabec
• [PATCH v5 04/13] dt-bindings: memory-controllers: add canaan k210 sram controller   Krzysztof Kozlowski
• [PATCH v5 04/13] dt-bindings: memory-controllers: add canaan k210 sram controller   Conor.Dooley at microchip.com
• [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree   Krzysztof Kozlowski
• [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree   Andre Przywara
• [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree   Krzysztof Kozlowski
• [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree   Krzysztof Kozlowski
• [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree   Conor.Dooley at microchip.com
• [PATCH 6/8] serial: Make ->set_termios() old ktermios const   Ilpo Järvinen
• [PATCH v8 0/4] Microchip soft ip corePWM driver   Conor Dooley
• [PATCH v8 1/4] dt-bindings: pwm: fix microchip corePWM's pwm-cells   Conor Dooley
• [PATCH v8 2/4] riscv: dts: fix the icicle's #pwm-cells   Conor Dooley
• [PATCH v8 3/4] pwm: add microchip soft ip corePWM driver   Conor Dooley
• [PATCH v8 4/4] MAINTAINERS: add pwm to PolarFire SoC entry   Conor Dooley
• Regression on Linux 6.0-rc1   Ron Economos
• [PATCH 0/3] Fix dt-validate issues on qemu dtbdumps due to dt-bindings   Andrew Jones
• [PATCH] rtc: mpfs: Remove printing of stray CR   Geert Uytterhoeven
• Regression on Linux 6.0-rc1   Dao Lu
• Regression on Linux 6.0-rc1   Anup Patel
• Regression on Linux 6.0-rc1   Conor.Dooley at microchip.com
• [PATCH v4] arch/riscv: add Zihintpause support   Palmer Dabbelt
• [PATCH v4] arch/riscv: add Zihintpause support   Conor.Dooley at microchip.com
• [PATCH v4] arch/riscv: add Zihintpause support   Andrew Jones
• [PATCH] riscv: Ensure isa-ext static keys are writable   Andrew Jones
• [PATCH] riscv: Ensure isa-ext static keys are writable   Conor.Dooley at microchip.com
• [PATCH] riscv: Ensure isa-ext static keys are writable   Andrew Jones
• [PATCH] riscv: Ensure isa-ext static keys are writable   Conor.Dooley at microchip.com
• [PATCH 4/4] dt-bindings: PCI: microchip,pcie-host: fix missing address translation property   Rob Herring
• [PATCH] rtc: mpfs: Remove printing of stray CR   Conor.Dooley at microchip.com
• [PATCH 02/12] dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles   Rob Herring
• [PATCH 03/12] dt-bindings: vendor-prefixes: Add Allwinner D1 board vendors   Rob Herring
• [PATCH 04/12] dt-bindings: riscv: Add Allwinner D1 board compatibles   Rob Herring
• [PATCH 4/4] dt-bindings: PCI: microchip,pcie-host: fix missing address translation property   Conor.Dooley at microchip.com
• [PATCH v2 0/6] Fix RISC-V/PCI dt-schema issues with dt-schema v2022.08   Conor Dooley
• [PATCH v2 1/6] dt-bindings: PCI: fu740-pci: fix missing clock-names   Conor Dooley
• [PATCH v2 2/6] dt-bindings: PCI: microchip,pcie-host: fix missing clocks properties   Conor Dooley
• [PATCH v2 3/6] riscv: dts: microchip: mpfs: fix incorrect pcie child node name   Conor Dooley
• [PATCH v2 4/6] riscv: dts: microchip: mpfs: remove ti,fifo-depth property   Conor Dooley
• [PATCH v2 5/6] riscv: dts: microchip: mpfs: remove bogus card-detect-delay   Conor Dooley
• [PATCH v2 6/6] riscv: dts: microchip: mpfs: remove pci axi address translation property   Conor Dooley
• [PATCH v5] perf arch events: riscv sbi firmware std event files   Arnaldo Carvalho de Melo
• [PATCH] riscv: Ensure isa-ext static keys are writable   Conor.Dooley at microchip.com
• RISC-V reserved memory problems   Conor.Dooley at microchip.com
• [PATCH v2 1/6] dt-bindings: PCI: fu740-pci: fix missing clock-names   Jessica Clarke
• [PATCH] riscv: Ensure isa-ext static keys are writable   Ron Economos
• [PATCH v2 1/6] dt-bindings: PCI: fu740-pci: fix missing clock-names   Conor.Dooley at microchip.com
• [PATCH 0/3] Fix dt-validate issues on qemu dtbdumps due to dt-bindings   Conor.Dooley at microchip.com
• [PATCH] riscv: Ensure isa-ext static keys are writable   Atish Patra
• [PATCH] riscv: Ensure isa-ext static keys are writable   Palmer Dabbelt
• [PATCH 0/3] Fix dt-validate issues on qemu dtbdumps due to dt-bindings   Andrew Jones
• Zwiększenie płynności finansowej   Jakub Olejniczak
• [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree   Krzysztof Kozlowski
• [PATCH] drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores   Heiko Stuebner
• [PATCH RESEND] drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores   Heiko Stuebner
• [PATCH v2 00/12] PolarFire SoC reset controller & clock cleanups   Conor.Dooley at microchip.com
• [PATCH 1/1] riscv: dts: microchip: correct L2 cache interrupts   Heinrich Schuchardt
• [PATCH v8 3/4] pwm: add microchip soft ip corePWM driver   kernel test robot
• [PATCH v8 3/4] pwm: add microchip soft ip corePWM driver   Conor.Dooley at microchip.com
• [PATCH] riscv: Ensure isa-ext static keys are writable   Jisheng Zhang
• [PATCH v8 27/31] Kbuild: add Rust support   Arnd Bergmann
• [PATCH v8 27/31] Kbuild: add Rust support   Miguel Ojeda
• [PATCH v8 27/31] Kbuild: add Rust support   Arnd Bergmann
• [PATCH] riscv: Ensure isa-ext static keys are writable   Andrew Jones
• [PATCH v8 27/31] Kbuild: add Rust support   Björn Roy Baron
• [PATCH V2 0/2] riscv: kexec: Fixup crash_save percpu and machine_kexec_mask_interrupts   guoren at kernel.org
• [PATCH V2 1/2] riscv: kexec: Disable all interrupts in kexec crash path   guoren at kernel.org
• [PATCH V2 2/2] riscv: kexec: Fixup crash_smp_send_stop with percpu crash_save_cpu   guoren at kernel.org
• [PATCH v2 00/12] PolarFire SoC reset controller & clock cleanups   Nathan Chancellor
• [PATCH 1/1] riscv: dts: microchip: correct L2 cache interrupts   Conor.Dooley at microchip.com
• [PATCH] drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores   Atish Patra
• [PATCH 0/4] Fix dt-validate issues on qemu dtbdumps due to dt-bindings   Conor Dooley
• [PATCH 1/4] dt-bindings: timer: sifive,clint: add legacy riscv compatible   Conor Dooley
• [PATCH 2/4] dt-bindings: interrupt-controller: sifive,plic: add legacy riscv compatible   Conor Dooley
• [PATCH 3/4] dt-bindings: riscv: add new riscv,isa strings for emulators   Conor Dooley
• [NOT-A-PATCH 4/4] dt-bindings: riscv: isa string bonus content   Conor Dooley
• [PATCH v2 0/4] Fix dt-validate issues on qemu dtbdumps due to dt-bindings   Conor Dooley
• [PATCH v2 1/4] dt-bindings: timer: sifive,clint: add legacy riscv compatible   Conor Dooley
• [PATCH v2 1/4] hw/riscv: virt: fix uart node name   Conor Dooley
• [PATCH 0/4] Fix dt-validate issues on qemu dtbdumps due to dt-bindings   Conor Dooley
• [PATCH v2 0/4] Fix dt-validate issues on qemu dtbdumps due to dt-bindings   Conor Dooley
• [PATCH v3 0/4] Fix dt-validate issues on qemu dtbdumps due to dt-bindings   Conor Dooley
• [PATCH v3 1/4] dt-bindings: timer: sifive,clint: add legacy riscv compatible   Conor Dooley
• [PATCH v3 2/4] dt-bindings: interrupt-controller: sifive,plic: add legacy riscv compatible   Conor Dooley
• [PATCH v3 3/4] dt-bindings: riscv: add new riscv,isa strings for emulators   Conor Dooley
• [NOT FOR INCLUSION v3 4/4] dt-bindings: riscv: isa string bonus content   Conor Dooley
• [PATCH 3/4] dt-bindings: riscv: add new riscv,isa strings for emulators   Andrew Jones
• [PATCH 3/4] dt-bindings: riscv: add new riscv,isa strings for emulators   Conor.Dooley at microchip.com
• [PATCH v8 27/31] Kbuild: add Rust support   Miguel Ojeda
• [PATCH v8 27/31] Kbuild: add Rust support   Miguel Ojeda
• [PATCH v3 3/4] dt-bindings: riscv: add new riscv,isa strings for emulators   Guo Ren
• [PATCH V2 1/2] riscv: kexec: Disable all interrupts in kexec crash path   Xianting Tian
• [PATCH V2 2/2] riscv: kexec: Fixup crash_smp_send_stop with percpu crash_save_cpu   Xianting Tian
• [PATCH v3 3/4] dt-bindings: riscv: add new riscv,isa strings for emulators   Andrew Jones
• [PATCH v3 3/4] dt-bindings: riscv: add new riscv,isa strings for emulators   Andrew Jones
• [PATCH v3 3/4] dt-bindings: riscv: add new riscv,isa strings for emulators   Conor.Dooley at microchip.com
• [PATCH 1/1] riscv: dts: microchip: correct L2 cache interrupts   Daire.McNamara at microchip.com
• [PATCH 2/2] riscv: kexec: Implement crash_smp_send_stop with percpu crash_save_cpu   kernel test robot
• [PATCH 1/1] riscv: dts: microchip: correct L2 cache interrupts   Heinrich Schuchardt
• [PATCH] drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores   Anup Patel
• [PATCH 1/1] riscv: dts: microchip: correct L2 cache interrupts   Conor.Dooley at microchip.com
• [PATCH 2/2] riscv: kexec: Implement crash_smp_send_stop with percpu crash_save_cpu   kernel test robot
• [PATCH v2 1/8] dt-bindings: riscv: Sort the CPU core list alphabetically   Geert Uytterhoeven
• [PATCH v2 1/8] dt-bindings: riscv: Sort the CPU core list alphabetically   Geert Uytterhoeven
• RISC-V reserved memory problems   Heinrich Schuchardt
• [PATCH v2 2/8] dt-bindings: riscv: Add Andes AX45MP core to the list   Geert Uytterhoeven
• [PATCH v2 3/8] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC   Geert Uytterhoeven
• [PATCH v2 2/6] dt-bindings: PCI: microchip,pcie-host: fix missing clocks properties   Rob Herring
• [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option   Geert Uytterhoeven
• [PATCH v2 2/6] dt-bindings: PCI: microchip,pcie-host: fix missing clocks properties   Conor.Dooley at microchip.com
• [PATCH v3 1/4] dt-bindings: timer: sifive,clint: add legacy riscv compatible   Rob Herring
• [PATCH v3 2/4] dt-bindings: interrupt-controller: sifive,plic: add legacy riscv compatible   Rob Herring
• [PATCH] riscv: dma-mapping: Use conventional cache operations for dma_sync*()   Sergei Miroshnichenko
• [PATCH] riscv: dma-mapping: Use conventional cache operations for dma_sync*()   Jessica Clarke
• [PATCH v2 3/8] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC   Lad, Prabhakar
• [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option   Lad, Prabhakar
• [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option   Conor.Dooley at microchip.com
• [PATCH 1/1] riscv: dts: microchip: correct L2 cache interrupts   Conor Dooley
• [PATCH] riscv: dma-mapping: Use conventional cache operations for dma_sync*()   Sergei Miroshnichenko
• [GIT PULL] Fix RISC-V's arch-topology reporting   Palmer Dabbelt
• [GIT PULL] Fix RISC-V's arch-topology reporting   Conor.Dooley at microchip.com
• [GIT PULL] Fix RISC-V's arch-topology reporting   Palmer Dabbelt
• [PATCH v3] RISC-V: Increase range and default value of NR_CPUS   Atish Patra
• [PATCH] riscv: dma-mapping: Use conventional cache operations for dma_sync*()   Jessica Clarke
• [PATCH] perf: riscv legacy: fix kerneldoc comment warning   Palmer Dabbelt
• [PATCH] riscv/vdso: fix missing vdso_data declaration   Palmer Dabbelt
• [PATCH 0/4] misc warning cleanup in arch/risc-v   Palmer Dabbelt
• [PATCH 2/2] riscv: kexec: Implement crash_smp_send_stop with percpu crash_save_cpu   Guo Ren
• [PATCH] kernel: exit: cleanup release_thread()   Kefeng Wang
• [PATCH] kernel: exit: cleanup release_thread()   Guo Ren
• [PATCH V3 0/3] riscv: kexec: Fixup crash_save percpu and machine_kexec_mask_interrupts   guoren at kernel.org
• [PATCH V3 1/3] riscv: kexec: Disable all interrupts in kexec crash path   guoren at kernel.org
• [PATCH V3 2/3] riscv: kexec: Fixup crash_smp_send_stop with percpu crash_save_cpu   guoren at kernel.org
• [PATCH V3 3/3] arch: crash: Remove duplicate declaration in smp.h   guoren at kernel.org
• [PATCH v2 1/2] riscv: ftrace: Fix the comments about the number of ftrace instruction   Li Huafei
• [PATCH v2 2/2] riscv: kprobe: Allow coexistence of ftrace and kprobe   Li Huafei
• [PATCH v4] arch/riscv: add Zihintpause support   Samuel Holland
• [PATCH] riscv/vdso: fix missing vdso_data declaration   Conor.Dooley at microchip.com
• [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option   Geert Uytterhoeven
• [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option   Conor.Dooley at microchip.com
• [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC   Geert Uytterhoeven
• [PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK   Geert Uytterhoeven
• [PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK   Geert Uytterhoeven
• [PATCH v2 7/8] MAINTAINERS: Add entry for Renesas RISC-V architecture   Geert Uytterhoeven
• [PATCH v2 8/8] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC   Geert Uytterhoeven
• [PATCH v9 0/4] Microchip soft ip corePWM driver   Conor Dooley
• [PATCH v9 1/4] dt-bindings: pwm: fix microchip corePWM's pwm-cells   Conor Dooley
• [PATCH v9 2/4] riscv: dts: fix the icicle's #pwm-cells   Conor Dooley
• [PATCH v9 3/4] pwm: add microchip soft ip corePWM driver   Conor Dooley
• [PATCH v9 4/4] MAINTAINERS: add pwm to PolarFire SoC entry   Conor Dooley
• [PATCH v2 7/8] MAINTAINERS: Add entry for Renesas RISC-V architecture   Lad, Prabhakar
• [PATCH] kernel: exit: cleanup release_thread()   Geert Uytterhoeven
• [PATCH v3 00/13] PolarFire SoC reset controller & clock cleanups   Conor Dooley
• [PATCH v3 01/13] clk: microchip: mpfs: fix clk_cfg array bounds violation   Conor Dooley
• [PATCH v3 02/13] dt-bindings: clk: microchip: mpfs: add reset controller support   Conor Dooley
• [PATCH v3 03/13] clk: microchip: mpfs: add reset controller   Conor Dooley
• [PATCH v3 04/13] reset: add polarfire soc reset support   Conor Dooley
• [PATCH v3 05/13] MAINTAINERS: add polarfire soc reset controller   Conor Dooley
• [PATCH v3 06/13] riscv: dts: microchip: add mpfs specific macb reset support   Conor Dooley
• [PATCH v3 07/13] clk: microchip: mpfs: add MSS pll's set & round rate   Conor Dooley
• [PATCH v3 08/13] clk: microchip: mpfs: move id & offset out of clock structs   Conor Dooley
• [PATCH v3 09/13] clk: microchip: mpfs: simplify control reg access   Conor Dooley
• [PATCH v3 10/13] clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo()   Conor Dooley
• [PATCH v3 11/13] clk: microchip: mpfs: convert cfg_clk to clk_divider   Conor Dooley
• [PATCH v3 12/13] clk: microchip: mpfs: convert periph_clk to clk_gate   Conor Dooley
• [PATCH v3 13/13] clk: microchip: mpfs: update module authorship & licencing   Conor Dooley
• [PATCH 0/4] misc warning cleanup in arch/risc-v   Conor.Dooley at microchip.com
• [PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK   Lad, Prabhakar
• [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC   Lad, Prabhakar
• [PATCH 0/6] Add PolarFire SoC Fabric Clock Conditioning Circuitry Support   Conor Dooley
• [PATCH 1/6] dt-bindings: clk: rename mpfs-clkcfg binding   Conor Dooley
• [PATCH 2/6] dt-bindings: clk: document PolarFire SoC fabric clocks   Conor Dooley
• [PATCH 3/6] dt-bindings: clk: add PolarFire SoC fabric clock ids   Conor Dooley
• [PATCH 4/6] clk: microchip: add PolarFire SoC fabric clock support   Conor Dooley
• [PATCH 5/6] dt-bindings: riscv: microchip: document icicle reference design   Conor Dooley
• [PATCH 6/6] riscv: dts: microchip: add the mpfs' fabric clock control   Conor Dooley
• [PATCH 1/6] dt-bindings: clk: rename mpfs-clkcfg binding   Krzysztof Kozlowski
• [PATCH 2/6] dt-bindings: clk: document PolarFire SoC fabric clocks   Krzysztof Kozlowski
• [PATCH 3/6] dt-bindings: clk: add PolarFire SoC fabric clock ids   Krzysztof Kozlowski
• [PATCH 5/6] dt-bindings: riscv: microchip: document icicle reference design   Krzysztof Kozlowski
• [PATCH 6/6] riscv: dts: microchip: add the mpfs' fabric clock control   Krzysztof Kozlowski
• [PATCH 6/6] riscv: dts: microchip: add the mpfs' fabric clock control   Conor.Dooley at microchip.com
• [PATCH 2/6] dt-bindings: clk: document PolarFire SoC fabric clocks   Conor.Dooley at microchip.com
• [PATCH 6/6] riscv: dts: microchip: add the mpfs' fabric clock control   Krzysztof Kozlowski
• [PATCH 6/6] riscv: dts: microchip: add the mpfs' fabric clock control   Conor.Dooley at microchip.com
• [PATCH 0/4] riscv: Introduce support for defining instructions   Andrew Jones
• [PATCH 1/4] riscv: Add X register names to gpr-nums   Andrew Jones
• [PATCH 2/4] riscv: Introduce support for defining instructions   Andrew Jones
• [PATCH 3/4] riscv: KVM: Apply insn-def to hfence encodings   Andrew Jones
• [PATCH 4/4] riscv: KVM: Apply insn-def to hlv encodings   Andrew Jones
• [PATCH 6/6] riscv: dts: microchip: add the mpfs' fabric clock control   Krzysztof Kozlowski
• [PATCH 6/6] riscv: dts: microchip: add the mpfs' fabric clock control   Conor.Dooley at microchip.com
• [PATCH 6/6] riscv: dts: microchip: add the mpfs' fabric clock control   Krzysztof Kozlowski
• [PATCH 2/4] riscv: Introduce support for defining instructions   Andrew Jones
• [PATCH 6/6] riscv: dts: microchip: add the mpfs' fabric clock control   Conor.Dooley at microchip.com
• [PATCH 6/6] riscv: dts: microchip: add the mpfs' fabric clock control   Krzysztof Kozlowski
• [PATCH] kernel: exit: cleanup release_thread()   Russell King (Oracle)
• [PATCH 1/4] riscv: kvm: vcpu_timer: fix unused variable warnings   Anup Patel
• [PATCH 2/4] riscv: kvm: move extern sbi_ext declarations to a header   Anup Patel
• [PATCH 0/4] misc warning cleanup in arch/risc-v   Anup Patel
• [GIT PULL] RISC-V Fixes for 6.0-rc2   Palmer Dabbelt
• [PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK   Conor.Dooley at microchip.com
• [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC   Conor.Dooley at microchip.com
• [PATCH 1/4] riscv: kvm: vcpu_timer: fix unused variable warnings   Atish Patra
• [GIT PULL] RISC-V Fixes for 6.0-rc2   pr-tracker-bot at kernel.org
• [PATCH 07/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree   Conor.Dooley at microchip.com
• [PATCH] MAINTAINERS: add PolarFire SoC dt bindings   Linus Walleij
• [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree   Conor.Dooley at microchip.com
• [PATCH] MAINTAINERS: add PolarFire SoC dt bindings   Conor.Dooley at microchip.com
• [PATCH v3 0/7] Fix RISC-V/PCI dt-schema issues with dt-schema v2022.08   Conor Dooley
• [PATCH v3 1/7] dt-bindings: PCI: fu740-pci: fix missing clock-names   Conor Dooley
• [PATCH v3 2/7] dt-bindings: PCI: microchip,pcie-host: fix missing clocks properties   Conor Dooley
• [PATCH v3 3/7] dt-bindings: PCI: microchip,pcie-host: fix missing dma-ranges   Conor Dooley
• [PATCH v3 4/7] riscv: dts: microchip: mpfs: fix incorrect pcie child node name   Conor Dooley
• [PATCH v3 5/7] riscv: dts: microchip: mpfs: remove ti,fifo-depth property   Conor Dooley
• [PATCH v3 6/7] riscv: dts: microchip: mpfs: remove bogus card-detect-delay   Conor Dooley
• [PATCH v3 7/7] riscv: dts: microchip: mpfs: remove pci axi address translation property   Conor Dooley
• RISC-V: patched kexec-tools on github for review/testing   Yixun Lan
• [PATCH v8 0/7] RISC-V IPI Improvements   Anup Patel
• [PATCH v8 1/7] RISC-V: Clear SIP bit only when using SBI IPI operations   Anup Patel
• [PATCH v8 2/7] irqchip/riscv-intc: Allow drivers to directly discover INTC hwnode   Anup Patel
• [PATCH v8 3/7] genirq: Add mechanism to multiplex a single HW IPI   Anup Patel
• [PATCH v8 4/7] RISC-V: Treat IPIs as normal Linux IRQs   Anup Patel
• [PATCH v8 5/7] RISC-V: Allow marking IPIs as suitable for remote FENCEs   Anup Patel
• [PATCH v8 6/7] RISC-V: Use IPIs for remote TLB flush when possible   Anup Patel
• [PATCH v8 7/7] RISC-V: Use IPIs for remote icache flush when possible   Anup Patel
• [GIT PULL] KVM/riscv fixes for 6.0, take #1   Anup Patel
• [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC   Geert Uytterhoeven
• [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC   Conor.Dooley at microchip.com
• [PATCH V3 3/3] arch: crash: Remove duplicate declaration in smp.h   Catalin Marinas
• [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC   Geert Uytterhoeven
• [PATCH AUTOSEL 5.19 08/48] riscv: dts: microchip: Add mpfs' topology information   Sasha Levin
• [PATCH] rtc: mpfs: Remove printing of stray CR   Conor.Dooley at microchip.com
• [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree   Samuel Holland
• [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree   Conor.Dooley at microchip.com
• [PATCH] kernel: exit: cleanup release_thread()   Brian Cain
• [RFC PATCH v1] riscv: make update_mmu_cache to support asid   Jinyu Tang
• Aanmelding vriend van De Hollekes: c2d2al   Beheer
• [RFC PATCH v1] riscv: make update_mmu_cache to support asid   Anup Patel
• [RFC PATCH v1] riscv: make update_mmu_cache to support asid   Anup Patel
• [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree   Icenowy Zheng
• [PATCH 07/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree   Icenowy Zheng
• [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree   Conor.Dooley at microchip.com
• [PATCH 0/6] Add an asm-generic cpuinfo_op declaration   Conor Dooley
• [PATCH 1/6] asm-generic: add a cpuinfo_ops definition in shared code   Conor Dooley
• [PATCH 2/6] microblaze: use the asm-generic version of cpuinfo_op   Conor Dooley
• [PATCH 3/6] s390: use the asm-generic version of cpuinfo_op   Conor Dooley
• [PATCH 4/6] sh: use the asm-generic version of cpuinfo_op   Conor Dooley
• [PATCH 5/6] sparc: use the asm-generic version of cpuinfo_op   Conor Dooley
• [PATCH 6/6] x86: use the asm-generic version of cpuinfo_op   Conor Dooley
• [PATCH 1/6] asm-generic: add a cpuinfo_ops definition in shared code   Conor.Dooley at microchip.com
• [PATCH] kernel: exit: cleanup release_thread()   Catalin Marinas
• [PATCH v6 RESEND 0/2] use static key to optimize pgtable_l4_enabled   Jisheng Zhang
• [PATCH v6 RESEND 1/2] riscv: move sbi_init() earlier before jump_label_init()   Jisheng Zhang
• [PATCH v6 RESEND 2/2] riscv: turn pgtable_l4|[l5]_enabled to static key for RV64   Jisheng Zhang
• [PATCH] riscv: compat: s/failed/unsupported if compat mode isn't supported   Jisheng Zhang
• [PATCH] riscv: compat: s/failed/unsupported if compat mode isn't supported   Guo Ren
• [PATCH] kernel: exit: cleanup release_thread()   Huacai Chen
• [PATCH] riscv: enable THP_SWAP for RV64   Jisheng Zhang
• [PATCH] kernel: exit: cleanup release_thread()   Stafford Horne
• [RFC 00/10] arm64/riscv: Introduce fast kexec reboot   Pingfan Liu
• [RFC 02/10] cpu/hotplug: Compile smp_shutdown_nonboot_cpus() conditioned on CONFIG_SHUTDOWN_NONBOOT_CPUS   Pingfan Liu
• [RFC 03/10] cpu/hotplug: Introduce fast kexec reboot   Pingfan Liu
• [RFC 04/10] cpu/hotplug: Check the capability of kexec quick reboot   Pingfan Liu
• [PATCH -next 0/2] riscv: ptrace: implement PTRACE_{PEEK,POKE}USR   Yipeng Zou
• [PATCH -next 1/2] riscv: ptrace: Implement PTRACE_{PEEK,POKE}USR   Yipeng Zou
• [PATCH -next 2/2] riscv: ptrace: Implement Compat PTRACE_{PEEK,POKE}USR   Yipeng Zou
• [PATCH v3 0/4] QEMU: Fix RISC-V virt & spike machines' dtbs   Alistair Francis
• [PATCH V3 0/9] Support RISCV64 arch and common commands   Yixun Lan
• [PATCH] riscv: enable THP_SWAP for RV64   Andrew Jones
• [PATCH -next 0/2] riscv: ptrace: implement PTRACE_{PEEK,POKE}USR   Andreas Schwab
• [PATCH v3 0/4] mm: arm64: bring up BATCHED_UNMAP_TLB_FLUSH   Yicong Yang
• [PATCH v3 1/4] Revert "Documentation/features: mark BATCHED_UNMAP_TLB_FLUSH doesn't apply to ARM64"   Yicong Yang
• [PATCH v3 2/4] mm/tlbbatch: Introduce arch_tlbbatch_should_defer()   Yicong Yang
• [PATCH v3 3/4] mm: rmap: Extend tlbbatch APIs to fit new platforms   Yicong Yang
• [PATCH v3 4/4] arm64: support batched/deferred tlb shootdown during page reclamation   Yicong Yang
• [PATCH v9 3/4] pwm: add microchip soft ip corePWM driver   Dan Carpenter
• [PATCH] selftests/seccomp: Check CAP_SYS_ADMIN capability in the test mode_filter_without_nnp   Gautam Menghani
• [PATCH v9 3/4] pwm: add microchip soft ip corePWM driver   Conor.Dooley at microchip.com
• [PATCH 0/6] Add an asm-generic cpuinfo_op declaration   Geert Uytterhoeven
• [PATCH 0/6] Add an asm-generic cpuinfo_op declaration   Conor.Dooley at microchip.com
• [PATCH 0/6] Add an asm-generic cpuinfo_op declaration   Geert Uytterhoeven
• [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree   Andre Przywara
• [PATCH v6 1/1] gpio: mpfs: add polarfire soc gpio support   Linus Walleij
• [PATCH v2 0/6] Add PolarFire SoC Fabric Clock Conditioning Circuitry Support   Conor Dooley
• [PATCH v2 1/6] dt-bindings: clk: rename mpfs-clkcfg binding   Conor Dooley
• [PATCH v2 2/6] dt-bindings: clk: document PolarFire SoC fabric clocks   Conor Dooley
• [PATCH v2 3/6] dt-bindings: clk: add PolarFire SoC fabric clock ids   Conor Dooley
• [PATCH v2 4/6] clk: microchip: add PolarFire SoC fabric clock support   Conor Dooley
• [PATCH v2 5/6] dt-bindings: riscv: microchip: document icicle reference design   Conor Dooley
• [PATCH v2 6/6] riscv: dts: microchip: add the mpfs' fabric clock control   Conor Dooley
• [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree   Geert Uytterhoeven
• [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree   Geert Uytterhoeven
• [PATCH v2 2/6] dt-bindings: clk: document PolarFire SoC fabric clocks   Conor.Dooley at microchip.com
• [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree   Conor.Dooley at microchip.com
• [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree   Andre Przywara
• [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree   Geert Uytterhoeven
• [PATCH v3 0/4] riscv, mm: detect svnapot cpu support at runtime   panqinglin2020 at iscas.ac.cn
• [PATCH v3 1/4] mm: modify pte format for Svnapot   panqinglin2020 at iscas.ac.cn
• [PATCH v3 2/4] mm: support Svnapot in physical page linear-mapping   panqinglin2020 at iscas.ac.cn
• [PATCH v3 3/4] mm: support Svnapot in hugetlb page   panqinglin2020 at iscas.ac.cn
• [PATCH v3 4/4] mm: support Svnapot in huge vmap   panqinglin2020 at iscas.ac.cn
• [PATCH v3 0/4] riscv, mm: detect svnapot cpu support at runtime   Conor.Dooley at microchip.com
• [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree   Conor.Dooley at microchip.com
• [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree   Jessica Clarke
• [PATCH v4 0/4] riscv, mm: detect svnapot cpu support at runtime   panqinglin2020 at iscas.ac.cn
• [PATCH v4 1/4] mm: modify pte format for Svnapot   panqinglin2020 at iscas.ac.cn
• [PATCH v4 2/4] mm: support Svnapot in physical page linear-mapping   panqinglin2020 at iscas.ac.cn
• [PATCH v4 3/4] mm: support Svnapot in hugetlb page   panqinglin2020 at iscas.ac.cn
• [PATCH v4 4/4] mm: support Svnapot in huge vmap   panqinglin2020 at iscas.ac.cn
• [PATCH v3 1/7] dt-bindings: PCI: fu740-pci: fix missing clock-names   Rob Herring
• [PATCH v3 2/7] dt-bindings: PCI: microchip,pcie-host: fix missing clocks properties   Rob Herring
• [PATCH v3 3/7] dt-bindings: PCI: microchip,pcie-host: fix missing dma-ranges   Rob Herring
• [PATCH v2 2/6] dt-bindings: clk: document PolarFire SoC fabric clocks   Rob Herring
• [PATCH v2 2/6] dt-bindings: clk: document PolarFire SoC fabric clocks   Conor.Dooley at microchip.com
• [PATCH v4 1/4] mm: modify pte format for Svnapot   Conor.Dooley at microchip.com
• [PATCH v4 1/4] mm: modify pte format for Svnapot   Conor.Dooley at microchip.com
• [PATCH v4 2/4] mm: support Svnapot in physical page linear-mapping   Conor.Dooley at microchip.com
• [PATCH v4 3/4] mm: support Svnapot in hugetlb page   Conor.Dooley at microchip.com
• [PATCH v4 4/4] mm: support Svnapot in huge vmap   Conor.Dooley at microchip.com
• [PATCH v4 0/4] riscv, mm: detect svnapot cpu support at runtime   Conor.Dooley at microchip.com
• [PATCH v2 2/6] dt-bindings: clk: document PolarFire SoC fabric clocks   Rob Herring
• [PATCH v2] RISC-V: Clean up the Zicbom block size probing   Conor.Dooley at microchip.com
• [PATCH v4 0/4] riscv, mm: detect svnapot cpu support at runtime   Qinglin Pan
• [PATCH v3 1/7] dt-bindings: PCI: fu740-pci: fix missing clock-names   Lorenzo Pieralisi
• RISC-V reserved memory problems   Conor.Dooley at microchip.com
• [PATCH v2 0/2] Fix console probe delay when stdout-path isn't set   Greg Kroah-Hartman
• [PATCH v4 0/4] Fix dt-validate issues on qemu dtbdumps due to dt-bindings   Conor Dooley
• [PATCH v4 1/4] dt-bindings: timer: sifive,clint: add legacy riscv compatible   Conor Dooley
• [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive,plic: add legacy riscv compatible   Conor Dooley
• [PATCH v4 3/4] dt-bindings: riscv: add new riscv,isa strings for emulators   Conor Dooley
• [PATCH v4 4/4] dt-bindings: riscv: isa string bonus content   Conor Dooley
• [PATCH 0/3] MPFS mailbox fixes   Conor.Dooley at microchip.com
• [PATCH 0/3] MPFS mailbox fixes   Jassi Brar
• [PATCH 0/3] MPFS mailbox fixes   Conor.Dooley at microchip.com
• [PATCH] rtc: mpfs: Remove printing of stray CR   Alexandre Belloni
• [PATCH v3 1/7] dt-bindings: PCI: fu740-pci: fix missing clock-names   Conor.Dooley at microchip.com
• [PATCH v3] clk: bcm2835: Round UART input clock up   Stephen Boyd
• [PATCH v2 0/2] Fix console probe delay when stdout-path isn't set   Saravana Kannan
• [PATCH v4 0/6] KVM: selftests: Implement ucall "pool" (for SEV)   Sean Christopherson
• [PATCH v4 1/6] KVM: selftests: Consolidate common code for populating ucall struct   Sean Christopherson
• [PATCH v4 2/6] KVM: selftests: Consolidate boilerplate code in get_ucall()   Sean Christopherson
• [PATCH v4 3/6] KVM: selftests: Automatically do init_ucall() for non-barebones VMs   Sean Christopherson
• [PATCH v4 4/6] tools: Add atomic_test_and_set_bit()   Sean Christopherson
• [PATCH v4 5/6] KVM: selftests: Make arm64's MMIO ucall multi-VM friendly   Sean Christopherson
• [PATCH v4 6/6] KVM: selftests: Add ucall pool based implementation   Sean Christopherson
• [PATCH -next v2 0/2]riscv: some refactorings realted to uaccess and extable   Tong Tiangen
• [PATCH v2 0/3] MPFS mailbox fixes   Conor Dooley
• [PATCH v2 1/3] dt-bindings: mailbox: fix the mpfs' reg property   Conor Dooley
• [PATCH v2 2/3] mailbox: mpfs: fix handling of the reg property   Conor Dooley
• [PATCH v2 3/3] mailbox: mpfs: account for mbox offsets while sending   Conor Dooley
• [PATCH v3] clk: bcm2835: Round UART input clock up   Ivan T. Ivanov
• [PATCH v3] clk: bcm2835: Round UART input clock up   Phil Elwell
• [PATCH] rtc: mpfs: Use devm_clk_get_enabled() helper   Christophe JAILLET
• [PATCH V3 0/9] Support RISCV64 arch and common commands   Xianting Tian
• [PATCH v10 0/4] Microchip soft ip corePWM driver   Conor Dooley
• [PATCH v10 1/4] dt-bindings: pwm: fix microchip corePWM's pwm-cells   Conor Dooley
• [PATCH v10 2/4] riscv: dts: fix the icicle's #pwm-cells   Conor Dooley
• [PATCH v10 3/4] pwm: add microchip soft ip corePWM driver   Conor Dooley
• [PATCH v10 4/4] MAINTAINERS: add pwm to PolarFire SoC entry   Conor Dooley
• [PATCH v3 0/5] Add PolarFire SoC Fabric Clock Conditioning Circuitry Support   Conor Dooley
• [PATCH v3 1/5] dt-bindings: clk: rename mpfs-clkcfg binding   Conor Dooley
• [PATCH v3 2/5] dt-bindings: clk: document PolarFire SoC fabric clocks   Conor Dooley
• [PATCH v3 3/5] dt-bindings: clk: add PolarFire SoC fabric clock ids   Conor Dooley
• [PATCH v3 4/5] clk: microchip: add PolarFire SoC fabric clock support   Conor Dooley
• [PATCH v3 5/5] riscv: dts: microchip: add the mpfs' fabric clock control   Conor Dooley
• [PATCH v3 2/4] mm/tlbbatch: Introduce arch_tlbbatch_should_defer()   Kefeng Wang
• [PATCH v3 3/4] mm: rmap: Extend tlbbatch APIs to fit new platforms   Kefeng Wang
• [PATCH v3 4/4] arm64: support batched/deferred tlb shootdown during page reclamation   Kefeng Wang
• [PATCH] rtc: mpfs: Use devm_clk_get_enabled() helper   Conor.Dooley at microchip.com
• [PATCH v3] clk: bcm2835: Round UART input clock up   Stefan Wahren
• [PATCH] rtc: mpfs: Use devm_clk_get_enabled() helper   Alexandre Belloni
• [PATCH] rtc: mpfs: Use devm_clk_get_enabled() helper   Christophe JAILLET
• (subset) [PATCH v3 0/7] Fix RISC-V/PCI dt-schema issues with dt-schema v2022.08   Lorenzo Pieralisi
• [PATCH] rtc: mpfs: Use devm_clk_get_enabled() helper   Conor.Dooley at microchip.com
• [PATCH net-next] driver: cadence macb driver support acpi mode   xiaowu.ding
• [PATCH] rtc: mpfs: Use devm_clk_get_enabled() helper   Conor.Dooley at microchip.com
• [PATCH] rtc: mpfs: Use devm_clk_get_enabled() helper   Alexandre Belloni
• [PATCH net-next] driver: cadence macb driver support acpi mode   Russell King (Oracle)
• [PATCH] rtc: mpfs: Use devm_clk_get_enabled() helper   Christophe JAILLET
• [PATCH v4 4/4] dt-bindings: riscv: isa string bonus content   Rob Herring
• [PATCH v3 2/5] dt-bindings: clk: document PolarFire SoC fabric clocks   Krzysztof Kozlowski
• [PATCH v4 5/6] KVM: selftests: Make arm64's MMIO ucall multi-VM friendly   Oliver Upton
• [PATCH net-next] driver: cadence macb driver support acpi mode   Andrew Lunn
• [PATCH net-next] driver: cadence macb driver support acpi mode   Andrew Lunn
• [PATCH v4 5/6] KVM: selftests: Make arm64's MMIO ucall multi-VM friendly   Sean Christopherson
• (subset) [PATCH v3 0/7] Fix RISC-V/PCI dt-schema issues with dt-schema v2022.08   Conor Dooley
• [PATCH -next v2 0/2]riscv: some refactorings realted to uaccess and extable   Conor.Dooley at microchip.com
• [PATCH v4 1/4] mm: modify pte format for Svnapot   Heiko Stübner
• [PATCH v4 3/4] dt-bindings: riscv: add new riscv,isa strings for emulators   Heiko Stübner
• [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive,plic: add legacy riscv compatible   Heiko Stübner
• [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive,plic: add legacy riscv compatible   Conor.Dooley at microchip.com
• [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive,plic: add legacy riscv compatible   Heiko Stübner
• [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive,plic: add legacy riscv compatible   Heiko Stübner
• [PATCH v4 1/4] dt-bindings: timer: sifive,clint: add legacy riscv compatible   Heiko Stübner
• [PATCH] drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores   Heiko Stuebner
• [PATCH] drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores   Anup Patel
• [PATCH -next v2 0/2]riscv: some refactorings realted to uaccess and extable   Tong Tiangen
• [PATCH -next v2 1/2] riscv: uaccess: rename __get/put_user_nocheck to __get/put_mem_nocheck   Andrew Jones
• [PATCH -next v2 2/2] riscv: extable: add new extable type EX_TYPE_KACCESS_ERR_ZERO support   Andrew Jones
• [PATCH 0/2] Add a PolarFire SoC l2 compatible   Conor Dooley
• [PATCH 1/2] dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible   Conor Dooley
• [PATCH 2/2] riscv: dts: microchip: use an mpfs specific l2 compatible   Conor Dooley
• [GIT PULL] Microchip RISC-V devicetree fixes for 6.0-rc3   Conor.Dooley at microchip.com
• [PATCH 1/2] dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible   Heinrich Schuchardt
• [PATCH 1/2] dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible   Conor.Dooley at microchip.com
• [PATCH 1/2] dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible   Heinrich Schuchardt
• [PATCH 2/2] riscv: dts: microchip: use an mpfs specific l2 compatible   Heinrich Schuchardt
• [PATCH 1/2] dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible   Conor.Dooley at microchip.com
• [PATCH v2] include/linux: declare cpuinfo_op in processor.h   Conor Dooley
• [PATCH v5 0/7] KVM: selftests: Implement ucall "pool" (for SEV)   Sean Christopherson
• [PATCH v5 1/7] KVM: selftests: Consolidate common code for populating ucall struct   Sean Christopherson
• [PATCH v5 2/7] KVM: selftests: Consolidate boilerplate code in get_ucall()   Sean Christopherson
• [PATCH v5 3/7] KVM: selftests: Automatically do init_ucall() for non-barebones VMs   Sean Christopherson
• [PATCH v5 4/7] tools: Add atomic_test_and_set_bit()   Sean Christopherson
• [PATCH v5 5/7] KVM: selftests: Make arm64's MMIO ucall multi-VM friendly   Sean Christopherson
• [PATCH v5 6/7] KVM: selftest: Drop now-unnecessary ucall_uninit()   Sean Christopherson
• [PATCH v5 7/7] KVM: selftests: Add ucall pool based implementation   Sean Christopherson
• [GIT PULL] Microchip RISC-V devicetree fixes for 6.0-rc3   Palmer Dabbelt
• [PATCH 0/4] misc warning cleanup in arch/risc-v   Palmer Dabbelt
• [RESEND PATCH 1/2] MAINTAINERS: add PolarFire SoC dt bindings   Palmer Dabbelt
• [RESEND/PULL PATCH 0/2] MAINTAINERS updates for PolarFire SoC   Palmer Dabbelt
• [PATCH v5 0/6] leds: Allwinner A100 LED controller support   Samuel Holland
• [PATCH v5 1/6] dt-bindings: leds: Add Allwinner A100 LED controller   Samuel Holland
• [PATCH v5 2/6] leds: sun50i-a100: New driver for the A100 LED controller   Samuel Holland
• [PATCH v5 3/6] arm64: dts: allwinner: a100: Add device node for DMA controller   Samuel Holland
• [PATCH v5 4/6] arm64: dts: allwinner: a100: Add LED controller node   Samuel Holland
• [PATCH v5 5/6] riscv: dts: allwinner: d1: Add LED controller node   Samuel Holland
• [PATCH v5 6/6] riscv: dts: allwinner: d1: Add RGB LEDs to boards   Samuel Holland
• [RESEND/PULL PATCH 0/2] MAINTAINERS updates for PolarFire SoC   Conor.Dooley at microchip.com
• [PATCH -next v2 1/2] riscv: uaccess: rename __get/put_user_nocheck to __get/put_mem_nocheck   Tong Tiangen
• [PATCH v3 4/5] clk: microchip: add PolarFire SoC fabric clock support   Claudiu.Beznea at microchip.com
• [PATCH -next v2 2/2] riscv: extable: add new extable type EX_TYPE_KACCESS_ERR_ZERO support   Tong Tiangen
• [PATCH v3 4/5] clk: microchip: add PolarFire SoC fabric clock support   Conor.Dooley at microchip.com
• [PATCH -next v2 1/2] riscv: uaccess: rename __get/put_user_nocheck to __get/put_mem_nocheck   Andrew Jones
• [PATCH -next v2 2/2] riscv: extable: add new extable type EX_TYPE_KACCESS_ERR_ZERO support   Andrew Jones
• [PATCH] MAINTAINERS: add PolarFire SoC dt bindings   Linus Walleij
• [PATCH -next v2 1/2] riscv: uaccess: rename __get/put_user_nocheck to __get/put_mem_nocheck   Arnd Bergmann
• [PATCH 0/9] New PolarFire SoC devkit devicetrees & 22.09 reference design updates   Conor Dooley
• [PATCH 1/9] dt-bindings: riscv: microchip: document icicle reference design   Conor Dooley
• [PATCH 2/9] dt-bindings: riscv: microchip: document the aries m100pfsevp   Conor Dooley
• [PATCH 3/9] dt-bindings: riscv: microchip: document the sev kit   Conor Dooley
• [PATCH 4/9] riscv: dts: microchip: add pci dma ranges for the icicle kit   Conor Dooley
• [PATCH 5/9] riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi   Conor Dooley
• [PATCH 6/9] riscv: dts: microchip: icicle: update pci address properties   Conor Dooley
• [PATCH 7/9] riscv: dts: microchip: icicle: re-jig fabric peripheral addresses   Conor Dooley
• [PATCH 8/9] riscv: dts: microchip: add sevkit device tree   Conor Dooley
• [PATCH 9/9] riscv: dts: microchip: add a devicetree for aries' m100pfsevp   Conor Dooley
• [RESEND/PULL PATCH 0/2] MAINTAINERS updates for PolarFire SoC   Palmer Dabbelt
• [PATCH 1/1] riscv: enable CD-ROM file systems in defconfig   Palmer Dabbelt
• [PATCH 5/6] sparc: use the asm-generic version of cpuinfo_op   Sam Ravnborg
• [PATCH] drivers/perf: riscv_pmu_sbi: add perf_user_access sysctl   Heiko Stuebner
• [PATCH 5/6] sparc: use the asm-generic version of cpuinfo_op   Conor.Dooley at microchip.com
• [GIT PULL] RISC-V Fixes for 6.0-rc3   Palmer Dabbelt
• [PATCH v2] drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores   Heiko Stuebner
• [PATCH] drivers/perf: riscv_pmu_sbi: add perf_user_access sysctl   Conor.Dooley at microchip.com
• [PATCH 5/6] sparc: use the asm-generic version of cpuinfo_op   Sam Ravnborg
• [PATCH v2] drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores   Conor.Dooley at microchip.com
• [PATCH v8 4/7] RISC-V: Treat IPIs as normal Linux IRQs   Conor.Dooley at microchip.com
• [PATCH v8 4/7] RISC-V: Treat IPIs as normal Linux IRQs   Marc Zyngier
• [GIT PULL] RISC-V Fixes for 6.0-rc3   pr-tracker-bot at kernel.org
• [PATCH v3 0/3] perf: RISC-V: misc fixes and improvements   Sergey Matyukevich
• [PATCH v3 1/3] perf: RISC-V: fix access beyond allocated array   Sergey Matyukevich
• [PATCH v3 2/3] perf: RISC-V: exclude invalid pmu counters from SBI calls   Sergey Matyukevich
• [PATCH v3 3/3] perf: RISC-V: throttle perf events   Sergey Matyukevich
• [PATCH v5 0/7] KVM: selftests: Implement ucall "pool" (for SEV)   Peter Gonda
• [PATCH v3 1/3] perf: RISC-V: fix access beyond allocated array   Conor.Dooley at microchip.com
• [PATCH 1/9] dt-bindings: riscv: microchip: document icicle reference design   Krzysztof Kozlowski
• [PATCH 2/9] dt-bindings: riscv: microchip: document the aries m100pfsevp   Krzysztof Kozlowski
• [PATCH 3/9] dt-bindings: riscv: microchip: document the sev kit   Krzysztof Kozlowski
• [PATCH v2] riscv: enable THP_SWAP for RV64   Jisheng Zhang
• [PATCH -next v2 2/2] riscv: extable: add new extable type EX_TYPE_KACCESS_ERR_ZERO support   Tong Tiangen
• [PATCH -next v2 1/2] riscv: uaccess: rename __get/put_user_nocheck to __get/put_mem_nocheck   Tong Tiangen
• [PATCH -next v2 1/2] riscv: uaccess: rename __get/put_user_nocheck to __get/put_mem_nocheck   Tong Tiangen
• [PATCH -next v2 1/2] riscv: uaccess: rename __get/put_user_nocheck to __get/put_mem_nocheck   Arnd Bergmann
• [PATCH v2] riscv: enable THP_SWAP for RV64   Conor.Dooley at microchip.com
• [PATCH] RISC-V: Add STACKLEAK erasing the kernel stack at the end of syscalls   Xianting Tian
• [PATCH v3 1/3] perf: RISC-V: fix access beyond allocated array   Sergey Matyukevich
• [PATCH v3 1/3] perf: RISC-V: fix access beyond allocated array   Conor.Dooley at microchip.com
• [PATCH -next v2 1/2] riscv: uaccess: rename __get/put_user_nocheck to __get/put_mem_nocheck   Tong Tiangen
• [PATCH] cpuidle: riscv-sbi: Fix CPU_PM_CPU_IDLE_ENTER_xyz() macro usage   Anup Patel
• [PATCH v8 4/7] RISC-V: Treat IPIs as normal Linux IRQs   Anup Patel
• [PATCH 0/3] Rename sifive L2 cache to sifive CCACHE   Zong Li
• [PATCH 1/3] dt-bindings: sifive-ccache: rename SiFive L2 cache to composible cache   Zong Li
• [PATCH 2/3] soc: sifive: l2 cache: Rename SiFive L2 cache to composible cache.   Zong Li
• [PATCH 3/3] EDAC/sifive: use sifive_ccache instead of sifive_l2   Zong Li
• [PATCH 1/3] dt-bindings: sifive-ccache: rename SiFive L2 cache to composible cache   Conor.Dooley at microchip.com
• [PATCH 2/3] soc: sifive: l2 cache: Rename SiFive L2 cache to composible cache.   Conor.Dooley at microchip.com
• [PATCH 1/3] dt-bindings: sifive-ccache: rename SiFive L2 cache to composible cache   Zong Li
• [PATCH 1/4] riscv: Add X register names to gpr-nums   Anup Patel
• [PATCH 2/4] riscv: Introduce support for defining instructions   Anup Patel
• [PATCH 3/4] riscv: KVM: Apply insn-def to hfence encodings   Anup Patel
• [PATCH 2/3] soc: sifive: l2 cache: Rename SiFive L2 cache to composible cache.   Zong Li
• [PATCH 4/4] riscv: KVM: Apply insn-def to hlv encodings   Anup Patel
• [PATCH 1/1] riscv: dts: microchip: correct L2 cache interrupts   Heinrich Schuchardt
• [PATCH 3/4] riscv: KVM: Apply insn-def to hfence encodings   Andrew Jones
• [PATCH 1/1] riscv: dts: microchip: correct L2 cache interrupts   Conor.Dooley at microchip.com
• [PATCH 0/4] Add PMEM support for RISC-V   Anup Patel
• [PATCH 1/4] RISC-V: Fix ioremap_cache() and ioremap_wc() for systems with Svpbmt   Anup Patel
• [PATCH 2/4] RISC-V: Move riscv_init_cbom_blocksize() to cacheflush.c   Anup Patel
• [PATCH 3/4] RISC-V: Implement arch specific PMEM APIs   Anup Patel
• [PATCH 4/4] RISC-V: Enable PMEM drivers   Anup Patel
• [PATCH v4] clk: bcm2835: Round UART input clock up   Ivan T. Ivanov
• [PATCH] dt-bindings: riscv: update microchip.yaml's maintainership   Conor Dooley
• [PATCH v2] riscv: enable THP_SWAP for RV64   Jisheng Zhang
• [PATCH v3] riscv: enable THP_SWAP for RV64   Jisheng Zhang
• [PATCH v5 3/7] KVM: selftests: Automatically do init_ucall() for non-barebones VMs   Andrew Jones
• [PATCH v5 5/7] KVM: selftests: Make arm64's MMIO ucall multi-VM friendly   Andrew Jones
• [PATCH v5 6/7] KVM: selftest: Drop now-unnecessary ucall_uninit()   Andrew Jones
• [PATCH v5 7/7] KVM: selftests: Add ucall pool based implementation   Andrew Jones
• [PATCH v2] riscv: enable THP_SWAP for RV64   Conor.Dooley at microchip.com
• [PATCH 0/4] Add PMEM support for RISC-V   Conor.Dooley at microchip.com
• [PATCH 1/3] dt-bindings: sifive-ccache: rename SiFive L2 cache to composible cache   Rob Herring
• [RFC PATCH 1/1] riscv: mm: notify remote harts about mmu cache updates   Sergey Matyukevich
• [PATCH 1/3] dt-bindings: sifive-ccache: rename SiFive L2 cache to composible cache   Zong Li
• [PATCH 3/4] riscv: KVM: Apply insn-def to hfence encodings   Anup Patel
• [PATCH v5 7/7] KVM: selftests: Add ucall pool based implementation   Sean Christopherson
• [PATCH 0/4] Add PMEM support for RISC-V   Anup Patel
• [PATCH v2 0/4] Add PMEM support for RISC-V   Anup Patel
• [PATCH v2 1/4] RISC-V: Fix ioremap_cache() and ioremap_wc() for systems with Svpbmt   Anup Patel
• [PATCH v2 2/4] RISC-V: Move riscv_init_cbom_blocksize() to cacheflush.c   Anup Patel
• [PATCH v2 3/4] RISC-V: Implement arch specific PMEM APIs   Anup Patel
• [PATCH v2 4/4] RISC-V: Enable PMEM drivers   Anup Patel
• [PATCH v6 1/1] gpio: mpfs: add polarfire soc gpio support   Lewis.Hanly at microchip.com
• [PATCH 0/4] Add PMEM support for RISC-V   Conor.Dooley at microchip.com
• [PATCH v3 03/13] clk: microchip: mpfs: add reset controller   Claudiu.Beznea at microchip.com
• [PATCH v3 03/13] clk: microchip: mpfs: add reset controller   Conor.Dooley at microchip.com
• [PATCH 0/3] arch: ptrace: Cleanup ptrace_disable   guoren at kernel.org
• [PATCH 1/3] riscv: ptrace: Remove duplicate operation   guoren at kernel.org
• [PATCH 2/3] openrisc: ptrace: Remove duplicate operation   guoren at kernel.org
• [PATCH 3/3] arch: ptrace: Cleanup ptrace_disable   guoren at kernel.org
• [PATCH 2/3] openrisc: ptrace: Remove duplicate operation   Stafford Horne
• [PATCH] riscv: Fix permissions for all mm's during mm init   Vladimir Isaev
• [PATCH 0/3] Rename sifive L2 cache to sifive CCACHE   Ben Dooks
• [PATCH 2/3] soc: sifive: l2 cache: Rename SiFive L2 cache to composible cache.   Ben Dooks
• [PATCH] riscv: Fix permissions for all mm's during mm init   Conor.Dooley at microchip.com
• [PATCH] soc: sifive: ccache: reduce printing on init   Ben Dooks
• [PATCH] riscv: Fix permissions for all mm's during mm init   Conor.Dooley at microchip.com
• [PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache   Ben Dooks
• [PATCH 2/3] soc: sifive: l2 cache: Rename SiFive L2 cache to composible cache.   Conor.Dooley at microchip.com
• [PATCH v2] riscv: Fix permissions for all mm's during mm init   Vladimir Isaev
• [PATCH] riscv: Fix permissions for all mm's during mm init   Vladimir Isaev
• [PATCH] dt-bindings: riscv: update microchip.yaml's maintainership   Krzysztof Kozlowski
• [PATCH v2 0/9] New PolarFire SoC devkit devicetrees & 22.09 reference design updates   Conor Dooley
• [PATCH v2 1/9] dt-bindings: riscv: microchip: document icicle reference design   Conor Dooley
• [PATCH v2 2/9] dt-bindings: riscv: microchip: document the aries m100pfsevp   Conor Dooley
• [PATCH v2 3/9] dt-bindings: riscv: microchip: document the sev kit   Conor Dooley
• [PATCH v2 4/9] riscv: dts: microchip: add pci dma ranges for the icicle kit   Conor Dooley
• [PATCH v2 5/9] riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi   Conor Dooley
• [PATCH v2 6/9] riscv: dts: microchip: icicle: update pci address properties   Conor Dooley
• [PATCH v2 7/9] riscv: dts: microchip: icicle: re-jig fabric peripheral addresses   Conor Dooley
• [PATCH v2 8/9] riscv: dts: microchip: add sevkit device tree   Conor Dooley
• [PATCH v2 9/9] riscv: dts: microchip: add a devicetree for aries' m100pfsevp   Conor Dooley
• [PATCH v2 6/9] riscv: dts: microchip: icicle: update pci address properties   Ben Dooks
• [PATCH v2] drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores   Heiko Stübner
• [PATCH v2 6/9] riscv: dts: microchip: icicle: update pci address properties   Conor.Dooley at microchip.com
• [PATCH v3 0/5] Add PolarFire SoC Fabric Clock Conditioning Circuitry Support   Conor Dooley
• [PATCH v3 1/5] dt-bindings: clk: rename mpfs-clkcfg binding   Conor Dooley
• [PATCH v3 2/5] dt-bindings: clk: document PolarFire SoC fabric clocks   Conor Dooley
• [PATCH v3 3/5] dt-bindings: clk: add PolarFire SoC fabric clock ids   Conor Dooley
• [PATCH v3 4/5] clk: microchip: add PolarFire SoC fabric clock support   Conor Dooley
• [PATCH v3 5/5] riscv: dts: microchip: add the mpfs' fabric clock control   Conor Dooley
• [PATCH v3 0/5] Add PolarFire SoC Fabric Clock Conditioning Circuitry Support   Conor.Dooley at microchip.com
• [PATCH v4 0/5] Add PolarFire SoC Fabric Clock Conditioning Circuitry Support   Conor Dooley
• [PATCH v4 1/5] dt-bindings: clk: rename mpfs-clkcfg binding   Conor Dooley
• [PATCH v4 2/5] dt-bindings: clk: document PolarFire SoC fabric clocks   Conor Dooley
• [PATCH v4 3/5] dt-bindings: clk: add PolarFire SoC fabric clock ids   Conor Dooley
• [PATCH v4 4/5] clk: microchip: add PolarFire SoC fabric clock support   Conor Dooley
• [PATCH v4 5/5] riscv: dts: microchip: add the mpfs' fabric clock control   Conor Dooley
• [PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache   Rob Herring
• [PATCH v4 00/13] PolarFire SoC reset controller & clock cleanups   Conor Dooley
• [RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache   Ben Dooks
• [PATCH v4 01/13] clk: microchip: mpfs: fix clk_cfg array bounds violation   Conor Dooley
• [PATCH v4 02/13] dt-bindings: clk: microchip: mpfs: add reset controller support   Conor Dooley
• [PATCH v4 03/13] clk: microchip: mpfs: add reset controller   Conor Dooley
• [PATCH v4 04/13] reset: add polarfire soc reset support   Conor Dooley
• [PATCH v4 05/13] MAINTAINERS: add polarfire soc reset controller   Conor Dooley
• [PATCH v4 06/13] riscv: dts: microchip: add mpfs specific macb reset support   Conor Dooley
• [PATCH v4 07/13] clk: microchip: mpfs: add MSS pll's set & round rate   Conor Dooley
• [PATCH v4 08/13] clk: microchip: mpfs: move id & offset out of clock structs   Conor Dooley
• [PATCH v4 09/13] clk: microchip: mpfs: simplify control reg access   Conor Dooley
• [PATCH v4 10/13] clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo()   Conor Dooley
• [PATCH v4 11/13] clk: microchip: mpfs: convert cfg_clk to clk_divider   Conor Dooley
• [PATCH v4 12/13] clk: microchip: mpfs: convert periph_clk to clk_gate   Conor Dooley
• [PATCH v4 13/13] clk: microchip: mpfs: update module authorship & licencing   Conor Dooley
• [RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache   Conor.Dooley at microchip.com
• [RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache   Ben Dooks
• [RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache   Conor.Dooley at microchip.com
• [PATCH v2] riscv: enable THP_SWAP for RV64   Jisheng Zhang
• [PATCH v2] riscv: enable THP_SWAP for RV64   Conor.Dooley at microchip.com
• [PATCH 0/3] arch: ptrace: Cleanup ptrace_disable   Oleg Nesterov
• [PATCH v2] riscv: enable THP_SWAP for RV64   Conor.Dooley at microchip.com
• [PATCH v2] riscv: enable THP_SWAP for RV64   Jisheng Zhang
• [PATCH v2] drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores   Heiko Stübner
• [PATCH v2 2/9] dt-bindings: riscv: microchip: document the aries m100pfsevp   Krzysztof Kozlowski
• [PATCH v2] drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores   Heiko Stübner
• [PATCH v2 2/9] dt-bindings: riscv: microchip: document the aries m100pfsevp   Conor.Dooley at microchip.com
• [PATCH v2] drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores   Conor.Dooley at microchip.com
• [PATCH v4 0/3] perf: RISC-V: misc fixes and improvements   Sergey Matyukevich
• [PATCH v4 1/3] perf: RISC-V: fix access beyond allocated array   Sergey Matyukevich
• [PATCH v4 2/3] perf: RISC-V: exclude invalid pmu counters from SBI calls   Sergey Matyukevich
• [PATCH v4 3/3] perf: RISC-V: throttle perf events   Sergey Matyukevich
• [PATCH] soc: sifive: ccache: reduce printing on init   Conor.Dooley at microchip.com
• [RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache   Ben Dooks
• [PATCH v2 2/9] dt-bindings: riscv: microchip: document the aries m100pfsevp   Krzysztof Kozlowski
• [PATCH v2 2/9] dt-bindings: riscv: microchip: document the aries m100pfsevp   Conor.Dooley at microchip.com
• [PATCH] soc: sifive: ccache: reduce printing on init   Ben Dooks
• [RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache   Conor.Dooley at microchip.com
• [PATCH v2 2/9] dt-bindings: riscv: microchip: document the aries m100pfsevp   Krzysztof Kozlowski
• [PATCH v2 2/9] dt-bindings: riscv: microchip: document the aries m100pfsevp   Conor.Dooley at microchip.com
• [PATCH v2 2/9] dt-bindings: riscv: microchip: document the aries m100pfsevp   Krzysztof Kozlowski
• [PATCH v2 2/9] dt-bindings: riscv: microchip: document the aries m100pfsevp   Conor.Dooley at microchip.com
• [PATCH v4 3/4] dt-bindings: riscv: add new riscv,isa strings for emulators   Rob Herring
• [PATCH] vdso: Improve cmd_vdso_check to check all dynamic relocations   Fangrui Song
• [PATCH 1/2] dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible   Rob Herring
• [PATCH 1/2] dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible   Rob Herring
• [PATCH] arch/riscv: kprobes: implement optprobes   Chen Guokai
• [RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache   Zong Li
• [PATCH] soc: sifive: ccache: reduce printing on init   Zong Li
• [PATCH 2/3] soc: sifive: l2 cache: Rename SiFive L2 cache to composible cache.   Zong Li
• [RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache   Conor.Dooley at microchip.com
• [PATCH] arch/riscv: kprobes: implement optprobes   Conor.Dooley at microchip.com
• [PATCH] arch/riscv: kprobes: implement optprobes   liaochang (A)
• [PATCH] arch/riscv: kprobes: implement optprobes   Conor.Dooley at microchip.com
• [PATCH] arch/riscv: kprobes: implement optprobes   Conor.Dooley at microchip.com
• [PATCH] arch/riscv: kprobes: implement optprobes   Conor.Dooley at microchip.com
• [PATCH] arch/riscv: kprobes: implement optprobes   chenguokai17 at mails.ucas.ac.cn
• [PATCH 0/3] Rename sifive L2 cache to sifive CCACHE   Zong Li
• Resend for Pure Text: Re: [PATCH] arch/riscv: kprobes: implement optprobes   Xim
• [PATCH] arch/riscv: kprobes: implement optprobes   liaochang (A)
• Resend for Pure Text: Re: [PATCH] arch/riscv: kprobes: implement optprobes   Conor.Dooley at microchip.com
• [PATCH] riscv:lib: optimize memcmp with ld insn   Yipeng Zou
• [PATCH] riscv:lib: optimize memcmp with ld insn   Conor.Dooley at microchip.com
• [PATCH v6 1/1] gpio: mpfs: add polarfire soc gpio support   Linus Walleij
• [PATCH] soc: sifive: ccache: reduce printing on init   Ben Dooks
• [PATCH 0/2] Add a PolarFire SoC l2 compatible   Conor Dooley
• [PATCH v4 01/13] clk: microchip: mpfs: fix clk_cfg array bounds violation   Conor.Dooley at microchip.com
• [PATCH v2 0/4] riscv: Introduce support for defining instructions   Andrew Jones
• [PATCH v2 1/4] riscv: Add X register names to gpr-nums   Andrew Jones
• [PATCH v2 2/4] riscv: Introduce support for defining instructions   Andrew Jones
• [PATCH v2 3/4] riscv: KVM: Apply insn-def to hfence encodings   Andrew Jones
• [PATCH v2 4/4] riscv: KVM: Apply insn-def to hlv encodings   Andrew Jones
• [PATCH v2 0/5] riscv: add PREEMPT_RT support   Jisheng Zhang
• [PATCH v2 1/5] RISC-V: KVM: Record number of signal exits as a vCPU stat   Jisheng Zhang
• [PATCH v2 2/5] RISC-V: KVM: Use generic guest entry infrastructure   Jisheng Zhang
• [PATCH v2 3/5] riscv: select HAVE_POSIX_CPU_TIMERS_TASK_WORK   Jisheng Zhang
• [PATCH v2 4/5] riscv: add lazy preempt support   Jisheng Zhang
• [PATCH v2 5/5] riscv: Allow to enable RT   Jisheng Zhang
• [PATCH v6 1/1] gpio: mpfs: add polarfire soc gpio support   Andy Shevchenko

Last message date: Wed Aug 31 14:04:40 PDT 2022
Archived on: Wed Aug 31 14:05:21 PDT 2022

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