[PATCH] riscv: dts: microchip: add qspi compatible fallback

[Conor Dooley]

The "hard" QSPI peripheral on PolarFire SoC is derived from version 2
of the FPGA IP core. The original binding had no fallback etc, so this
device tree is valid as is. There was also no functional driver for the
QSPI IP, so no device with a devicetree from a previous mainline
release will regress.

Link: https://lore.kernel.org/linux-spi/7c9f0d96-2882-964a-cd1f-916ddb3f0410@linaro.org/
Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
---
See the link for binding discussion. I'll apply this at some point once
the driver makes it upstream.

CC: nagasuresh.relli at microchip.com
CC: valentina.fernandezalanis at microchip.com
CC: broonie at kernel.org
CC: devicetree at vger.kernel.org
CC: krzysztof.kozlowski+dt at linaro.org
CC: robh+dt at kernel.org
CC: linux-kernel at vger.kernel.org
CC: linux-spi at vger.kernel.org
CC: linux-riscv at lists.infradead.org
---
 arch/riscv/boot/dts/microchip/mpfs.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index 499c2e63ad35..45e3cc659882 100644
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -330,7 +330,7 @@ spi1: spi at 20109000 {
 		};
 
 		qspi: spi at 21000000 {
-			compatible = "microchip,mpfs-qspi";
+			compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x0 0x21000000 0x0 0x1000>;
-- 
2.36.1