[PATCH 2/2] riscv: dts: microchip: use an mpfs specific l2 compatible

[Heinrich Schuchardt]

On 8/25/22 20:04, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley at microchip.com>
> 
> PolarFire SoC does not have the same l2 cache controller as the fu540,
> featuring an extra interrupt. Appease the devicetree checker overlords
> by adding a PolarFire SoC specific compatible to fix the below sort of
> warnings:
> 
> mpfs-polarberry.dtb: cache-controller at 2010000: interrupts: [[1], [3], [4], [2]] is too long
> 
> Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")
> Fixes: 34fc9cc3aebe ("riscv: dts: microchip: correct L2 cache interrupts")
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>

Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>