[PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK

[Palmer Dabbelt]

On Thu, 11 Aug 2022 23:23:10 PDT (-0700), krzysztof.kozlowski at linaro.org wrote:
> On 11/08/2022 18:42, Geert Uytterhoeven wrote:
>> At the DT validation level, I think the proper solution is to
>> merge Documentation/devicetree/bindings/arm/renesas.yaml and
>> Documentation/devicetree/bindings/riscv/renesas.yaml into a single
>> file under Documentation/devicetree/bindings/soc/renesas/.
>>
>> What do other people think?
>
> I am ok with it.

Seems reasonable to me too, but I pretty much always err on the side of 
keeping SOC stuff split out from the RISC-V stuff.  Just looking at 
Documentation/devicetree/bindings/riscv/, it's pretty much all SOC stuff 
-- should we just move everything but cpus.yaml over?