[PATCH 1/5] target/riscv: Ignore the S and U letters when formatting ISA strings
Tsukasa OI
research_trasio at irq.a4lg.com
Mon Aug 8 08:03:12 PDT 2022
On 2022/08/06 0:54, Conor Dooley wrote:
> From: Palmer Dabbelt <palmer at sifive.com>
>
> The ISA strings we're providing from QEMU aren't actually legal RISC-V
> ISA strings, as both S and U cannot exist as single-letter extensions
> and must instead be multi-letter strings. We're still using the ISA
> strings inside QEMU to track the availiable extensions, so just strip
> out the S and U extensions when formatting ISA strings.
>
> Signed-off-by: Palmer Dabbelt <palmer at sifive.com>
> [Conor: rebased on 7.1.0-rc1 & slightly tweaked the commit message]
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> ---
> target/riscv/cpu.c | 18 +++++++++++++++++-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index ac6f82ebd0..95fdc03b3d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1122,7 +1122,23 @@ char *riscv_isa_string(RISCVCPU *cpu)
> char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
> for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) {
> if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) {
> - *p++ = qemu_tolower(riscv_single_letter_exts[i]);
> + char lower = qemu_tolower(riscv_single_letter_exts[i]);
> + switch (lower) {
> + case 's':
> + case 'u':
> + /*
> + * The 's' and 'u' letters shouldn't show up in ISA strings as
> + * they're not extensions, but they should show up in MISA.
> + * Since we use these letters interally as a pseudo ISA string
> + * to set MISA it's easier to just strip them out when
> + * formatting the ISA string.
> + */
> + break;
> +
> + default:
> + *p++ = lower;
> + break;
> + }
> }
> }
> *p = '\0';
I agree with Alistair. **I** removed 'S' and 'U' from the ISA string
and it should be working in the latest development branch (I tested).
I tested it on master and QEMU 7.1-rc1 (tag: v7.1-rc1).
Example:
/opt/riscv/bin/qemu-system-riscv64
-machine virt
-nographic
-cpu rv64
-smp 1
-kernel images/linux.bin
-initrd images/busybox.cpio.gz
-append 'console=hvc0 earlycon=sbi'
-bios images/opensbi-fw_jump.elf
-gdb tcp::9000
Replacing -machine virt with -machine virt,dumpdtb=sample.dtb dumps the
binary DeviceTree as sample.dtb and generated CPU-related parts like...
cpu at 0 {
phandle = <0x01>;
device_type = "cpu";
reg = <0x00>;
status = "okay";
compatible = "riscv";
riscv,isa =
"rv64imafdch_zicsr_zifencei_zba_zbb_zbc_zbs";
mmu-type = "riscv,sv48";
interrupt-controller {
#interrupt-cells = <0x01>;
interrupt-controller;
compatible = "riscv,cpu-intc";
phandle = <0x02>;
};
};
Besides, this function alone generates the ISA string for DTB and
there's no way such ISA strings with invalid 'S' and 'U' can be
generated. It's definitely a behavior of QEMU 7.0 or before.
Please. Please make sure that you are testing the right version of QEMU.
Thanks,
Tsukasa
More information about the linux-riscv
mailing list