[PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

[Conor.Dooley at microchip.com]

On 22/08/2022 13:31, Geert Uytterhoeven wrote:
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>> Do you think this is worth doing? Or are you just providing an
>> example of what could be done?
> 
> Just some brainstorming...
> 
>> Where would you envisage putting these macros? I forget the order
>> of the CPP operations that are done, can they be put in the dts?
> 
> The SOC_PERIPHERAL_IRQ() macro should be defined in the
> ARM-based SoC.dtsi file and the RISC-V-based SoC.dtsi file.

Right, one level up but ~the same result.


>>> Nice! But it's gonna be a very large interrupt-map.
>>
>> I quite like the idea of not duplicating files across the archs
>> if it can be helped, but not at the expense of making them hard to
>> understand & I feel like unfortunately the large interrupt map is
>> in that territory.
> 
> I feel the same.
> Even listing both interrupt numbers in SOC_PERIPHERAL_IRQ(na, nr)
> is a risk for making mistakes.
> 
> So personally, I'm in favor of teaching dtc arithmetic, so we can
> handle the offset in SOC_PERIPHERAL_IRQ().

Yup, in the same boat here. mayb I'll get bored enough to bite..