[PATCH v2 2/6] dt-bindings: clk: document PolarFire SoC fabric clocks

[Rob Herring]

On Mon, Aug 22, 2022 at 07:44:20PM +0000, Conor.Dooley at microchip.com wrote:
> On 22/08/2022 20:40, Rob Herring wrote:
> > On Mon, 22 Aug 2022 12:29:25 +0100, Conor Dooley wrote:
> >> On PolarFire SoC there are 4 PLL/DLL blocks, located in each of the
> >> ordinal corners of the chip, which our documentation refers to as
> >> "Clock Conditioning Circuitry". PolarFire SoC is an FPGA, these are
> >> highly configurable & many of the input clocks are optional.
> >>
> >> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> >> ---
> >>  .../bindings/clock/microchip,mpfs-ccc.yaml    | 81 +++++++++++++++++++
> >>  1 file changed, 81 insertions(+)
> >>  create mode 100644 Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml
> >>
> > 
> > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> > on your patch (DT_CHECKER_FLAGS is new in v5.13):
> 
> Heh, been waiting for this one all day. Messed up squashing commits
> before sending v2... fixed locally & I'll respin later in the week.
> I tried to mark it "changes required" in patchwork so you'd not waste
> time on it but I think that got reverted?

Could have. The CI job messes with the state and then I do, and my 
scripts don't expect the state changing underneath it. Most users don't 
have PW accounts.

Don't worry, I don't spend much time on failing patches.

Rob