Help for doubt about why update SCTLR by cr_alignment every syscall,IRQ,exception ?
wuqixuan at huawei.com
Tue Apr 15 05:54:29 PDT 2014
On Tue, Apr 14, 2014 at 03:30:00AM +0000, Russell King wrote:
>> Second question is important for us, because the instruction of
>> updation is too slow(about 100 cycles) in our chip, we want to remove
>> the updation instruction for low latency reason, so need your opinion.
> What about it is slow - is the 100 cycles from the mcr itself?
Yes, in our ARMv7 Cortex A15 SOC, only single mcr instruction need
about 100 cycles, so we want to remove it.
Can you help to give some idea about the risk to remove it ?
Regards and Thanks a lot.
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