L2 cache suspend/resume

[Russell King - ARM Linux]

While looking through the L2 resume code paths, I notice that:

 * exynos
 * imx
 * tegra

all resume their L2 caches from assembly code, rather than using
outer_disable() before cpu_suspend(), and outer_resume() afterwards.
>From what I can see, these are all running in the secure world, so that
isn't the reason.

What is the reason for this difference?  Can these three be converted to
the outer_disable()...outer_resume() method?

-- 
FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.