Help for doubt about why update SCTLR by cr_alignment every syscall,IRQ,exception ?

Russell King - ARM Linux linux at
Sun Apr 13 12:29:30 PDT 2014

On Tue, Apr 08, 2014 at 03:46:38AM +0000, Wuqixuan wrote:
> Second question is important for us, because the instruction of
> updation is too slow(about 100 cycles) in our chip, we want to remove
> the updation instruction for low latency reason, so need your opinion. 

What about it is slow - is the 100 cycles from the mcr itself?

FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.

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