[PATCH] sdhci: add support for H/W clock gating of SD controller

[Philip Rakity]

MMP2 controller allows clock gating for SD/eMMC/SDIO cards
by extending the definition for SDCTRL_2_ASYNC_INT_EN in the
host control register 2. The SD Host Controller spec
defines this bit (14) for use with SDIO.

Use standard values in sdhci.h for register.

Signed-off-by: Philip Rakity <prakity at marvell.com>
Signed-off-by: Mark F. Brown <markb at marvell.com>
Tested-by: Philip Rakity
---
 drivers/mmc/host/sdhci-mmp2.c |    5 ++---
 1 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/host/sdhci-mmp2.c b/drivers/mmc/host/sdhci-mmp2.c
index 6824177..7303421 100644
--- a/drivers/mmc/host/sdhci-mmp2.c
+++ b/drivers/mmc/host/sdhci-mmp2.c
@@ -39,7 +39,6 @@
=20
 #define DRIVER_NAME "sdhci-mmp2"
=20
-#define HOST_CTRL_2		0x3E
 #define ASYNC_INT_EN		(1 << 14)
=20
 #define SD_CFG_FIFO_PARAM       0x100
@@ -148,9 +147,9 @@ static void programFIFO(struct sdhci_host *host, int en=
able)
 	tmp =3D readw(host->ioaddr + HOST_CTRL_2);
=20
 	if (enable)
-		tmp |=3D ASYNC_INT_EN;
+		tmp |=3D SDCTRL_2_ASYNC_INT_EN;
 	else
-		tmp &=3D ~ASYNC_INT_EN;
+		tmp &=3D ~SDCTRL_2_ASYNC_INT_EN;
=20
 	writew(tmp, host->ioaddr + HOST_CTRL_2);
 }
--=20
1.6.0.4

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