[PATCH] ARM: Rockchip: Update DTS for BPI-R2Pro for new HW-Rev

Sascha Hauer s.hauer at pengutronix.de
Thu Apr 14 00:34:22 PDT 2022


On Mon, Apr 11, 2022 at 01:44:47PM +0200, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w at public-files.de>
> 
> New Hardware revision swapped the gmacs (wan is now gmac1).
> Previous Revision (v00) was not in public sale so devicetree
> can be savely changed.
> 
> Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
> ---
>  arch/arm/dts/rk3568-bpi-r2-pro.dts | 28 ++++++++++++++--------------
>  1 file changed, 14 insertions(+), 14 deletions(-)

Applied, thanks

Sascha

> 
> diff --git a/arch/arm/dts/rk3568-bpi-r2-pro.dts b/arch/arm/dts/rk3568-bpi-r2-pro.dts
> index ef2e0c33e663..cc1bab37074a 100644
> --- a/arch/arm/dts/rk3568-bpi-r2-pro.dts
> +++ b/arch/arm/dts/rk3568-bpi-r2-pro.dts
> @@ -120,20 +120,20 @@
>  	};
>  };
>  
> -&gmac0 {
> -	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
> -	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
> -	assigned-clock-rates = <0>, <125000000>;
> -	clock_in_out = "input";
> -	phy-handle = <&rgmii_phy0>;
> +&gmac1 {
> +	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
> +	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
> +	clock_in_out = "output";
> +	phy-handle = <&rgmii_phy1>;
>  	phy-mode = "rgmii";
>  	pinctrl-names = "default";
> -	pinctrl-0 = <&gmac0_miim
> -		     &gmac0_tx_bus2
> -		     &gmac0_rx_bus2
> -		     &gmac0_rgmii_clk
> -		     &gmac0_rgmii_bus>;
> -	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
> +	pinctrl-0 = <&gmac1m1_miim
> +		     &gmac1m1_tx_bus2
> +		     &gmac1m1_rx_bus2
> +		     &gmac1m1_rgmii_clk
> +		     &gmac1m1_rgmii_bus>;
> +
> +	snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
>  	snps,reset-active-low;
>  	/* Reset time is 20ms, 100ms for rtl8211f */
>  	snps,reset-delays-us = <0 20000 100000>;
> @@ -367,8 +367,8 @@
>  	status = "disabled";
>  };
>  
> -&mdio0 {
> -	rgmii_phy0: ethernet-phy at 0 {
> +&mdio1 {
> +	rgmii_phy1: ethernet-phy at 0 {
>  		compatible = "ethernet-phy-ieee802.3-c22";
>  		reg = <0x0>;
>  	};
> -- 
> 2.25.1
> 
> 

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