[PATCH 4/7] arm: initial support for Marvell Armada 370/XP SoCs

[Sascha Hauer]

On Mon, May 06, 2013 at 04:34:24PM +0200, Thomas Petazzoni wrote:
> Dear Sascha Hauer,
> 
> On Mon, 6 May 2013 16:30:30 +0200, Sascha Hauer wrote:
> 
> > > ... and here, I'm directly poking at physical addresses, but it seems
> > > like Barebox can run with the MMU enabled. Should I be mapping those
> > > registers before accessing them?
> > 
> > We use the MMU, but we use a 1:1 mapping. The SDRAM is mapped cached and
> > the rest is mapped uncached. This means you can simply access all
> > registers without mapping them
> 
> Ok, thanks. So you're not overly chocked by those readl() poking
> directly at physical addresses, if I understand correctly.

Not at all, we do this everywhere. There is a tendency to turn units
into proper drivers though as drivers show up in the 'iomem' command and
with drivers it's generally easier to abstract between different SoCs.

Sascha


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