[PATCH 4/7] arm: initial support for Marvell Armada 370/XP SoCs

[Thomas Petazzoni]

Dear Sascha Hauer,

On Mon, 6 May 2013 16:30:30 +0200, Sascha Hauer wrote:

> > ... and here, I'm directly poking at physical addresses, but it seems
> > like Barebox can run with the MMU enabled. Should I be mapping those
> > registers before accessing them?
> 
> We use the MMU, but we use a 1:1 mapping. The SDRAM is mapped cached and
> the rest is mapped uncached. This means you can simply access all
> registers without mapping them

Ok, thanks. So you're not overly chocked by those readl() poking
directly at physical addresses, if I understand correctly.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com