[PATCH 4/7] arm: initial support for Marvell Armada 370/XP SoCs

[Thomas Petazzoni]

Dear Sascha Hauer,

On Mon, 6 May 2013 16:46:34 +0200, Sascha Hauer wrote:

> > > We use the MMU, but we use a 1:1 mapping. The SDRAM is mapped cached and
> > > the rest is mapped uncached. This means you can simply access all
> > > registers without mapping them
> > 
> > Ok, thanks. So you're not overly chocked by those readl() poking
> > directly at physical addresses, if I understand correctly.
> 
> Not at all, we do this everywhere. There is a tendency to turn units
> into proper drivers though as drivers show up in the 'iomem' command and
> with drivers it's generally easier to abstract between different SoCs.

Ok. The code in this patch is really an initial support, and I expect
the clock and DRAM stuff to evolve as support for other Marvell SOCs
will be added, or for additional devices.

Thanks,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com