[PATCH 24/25] riscv: add Metanoia MT2824 SoC and MT5824 EVB support
Conor Dooley
conor at kernel.org
Fri Nov 6 10:30:30 PST 2026
On Fri, Nov 06, 2026 at 10:30:21AM +0100, Benoît Monin wrote:
> Add the device tree for the Metanoia MT2824, a dual-core Andes
> AX45MP-based SoC, and for the MT5824 evaluation board.
>
> The SoC device tree describes the CPUs and their L2 cache, the PLIC,
> PLICSW and PLMT, the reset controller, the reboot controller, the
> watchdog, two UARTs, the QSPI and eight SPI controllers, the DWC
> MSHC MMC controller, and the USB2 controller.
>
> The MT5824 EVB enables the watchdog, the two UARTs, the MMC
> controller, the QSPI port with its SPI-NOR flash, the first three SPI
> controllers, and the USB controller.
>
> Originally-by: Jun Chang <jun.chang at metanoia-comm.com>
> Signed-off-by: Benoît Monin <benoit.monin at bootlin.com>
> ---
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/metanoia/Makefile | 2 +
> arch/riscv/boot/dts/metanoia/mt2824.dtsi | 330 ++++++++++++++++++++++++++++
> arch/riscv/boot/dts/metanoia/mt5824-evb.dts | 81 +++++++
> 4 files changed, 414 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index 69d8751fb17c..8e1e987ea089 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -4,6 +4,7 @@ subdir-y += andes
> subdir-y += anlogic
> subdir-y += canaan
> subdir-y += eswin
> +subdir-y += metanoia
> subdir-y += microchip
> subdir-y += renesas
> subdir-y += sifive
> diff --git a/arch/riscv/boot/dts/metanoia/Makefile b/arch/riscv/boot/dts/metanoia/Makefile
> new file mode 100644
> index 000000000000..7a685798d5a4
> --- /dev/null
> +++ b/arch/riscv/boot/dts/metanoia/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_METANOIA) += mt5824-evb.dtb
> diff --git a/arch/riscv/boot/dts/metanoia/mt2824.dtsi b/arch/riscv/boot/dts/metanoia/mt2824.dtsi
> new file mode 100644
> index 000000000000..5f73c6d3760b
> --- /dev/null
> +++ b/arch/riscv/boot/dts/metanoia/mt2824.dtsi
> @@ -0,0 +1,330 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2026 Metanoia Communications Inc.. All rights reserved.
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + #address-cells = <0x02>;
> + #size-cells = <0x02>;
> + compatible = "metanoia,mt2824";
> +
> + cpus: cpus {
> + #address-cells = <0x01>;
> + #size-cells = <0x00>;
Non-hex here please.
> + timebase-frequency = <20000000>;
> +
> + cpu0: cpu at 0 {
> + device_type = "cpu";
> + reg = <0x00>;
0x0 etc
> + compatible = "andestech,ax45mp", "riscv";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> + "zicntr", "zicsr", "zifencei",
> + "zihpm", "xandespmu";
> + mmu-type = "riscv,sv39";
> + clock-frequency = <900000000>;
> + i-cache-size = <0x8000>;
> + i-cache-sets = <0x100>;
> + i-cache-line-size = <0x40>;
> + i-cache-block-size = <0x40>;
> + d-cache-size = <0x8000>;
> + d-cache-sets = <0x80>;
> + d-cache-line-size = <0x40>;
> + d-cache-block-size = <0x40>;
> + next-level-cache = <&l2_cache>;
> +
> + cpu0intc: interrupt-controller {
> + #interrupt-cells = <0x01>;
> + interrupt-controller;
> + compatible = "andestech,cpu-intc", "riscv,cpu-intc";
> + };
> + };
> +
> + cpu1: cpu at 1 {
> + device_type = "cpu";
> + reg = <0x01>;
> + compatible = "andestech,ax45mp", "riscv";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> + "zicntr", "zicsr", "zifencei",
> + "zihpm", "xandespmu";
> + mmu-type = "riscv,sv39";
> + clock-frequency = <900000000>;
> + i-cache-size = <0x8000>;
> + i-cache-sets = <0x100>;
> + i-cache-line-size = <0x40>;
> + i-cache-block-size = <0x40>;
> + d-cache-size = <0x8000>;
> + d-cache-sets = <0x80>;
> + d-cache-line-size = <0x40>;
> + d-cache-block-size = <0x40>;
> + next-level-cache = <&l2_cache>;
> +
> + cpu1intc: interrupt-controller {
> + #interrupt-cells = <0x01>;
> + interrupt-controller;
> + compatible = "andestech,cpu-intc", "riscv,cpu-intc";
> + };
> + };
> + };
> +
> + clocks {
> + ext_clk: ext-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <20000000>;
> + clock-output-names = "ext-clk";
> + };
Is the frequency here actually set by the soc, or actually by the board?
If it says "ext", I assume it's not part of the soc.
> +
> + pclk_div4: platform-clock-div4 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <225000000>;
> + clock-output-names = "platform-clock-div4";
> + };
> +
> + pll_soc_out3: pll-soc-out3 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <180000000>;
> + clock-output-names = "pll-soc-out3";
> + };
> +
> + usb_otg_ahb_clk: clock-usb-otg-ahb {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <60000000>;
> + clock-output-names = "otg";
> + };
I'd much rather this not be merged until things like this are replaced
by an actual clock controller, lest it appear in u-boot etc and then
have the support break because it got swapped out for a clock
controller.
> + };
> +
> + soc: soc {
> + #address-cells = <0x02>;
> + #size-cells = <0x02>;
> + compatible = "simple-bus";
> + interrupt-parent = <&plic>;
> + ranges;
> +
> + usb0: usb at 4000000 {
> + compatible = "metanoia,mt2824-usb", "snps,dwc2";
> + reg = <0x0 0x04000000 0x0 0x100000>;
> + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&usb_otg_ahb_clk>;
> + clock-names = "otg";
> + dr_mode = "host";
> + resets = <&rst 19>, <&rst 20>;
> + reset-names = "dwc2", "dwc2-ecc";
> + phys = <&usb2phy>;
> + phy-names = "usb2-phy";
> + hnp-disable;
> + srp-disable;
> + disable-over-current;
> + status = "disabled";
> + };
> +
> + mmcsd: mmc at 4100000 {
> + compatible = "metanoia,mt2824-dwcmshc";
> + clocks = <&pll_soc_out3>;
> + clock-names = "core";
> + reg = <0x0 0x04100000 0x0 0x00100000>;
ordering should be compatible -> reg
> + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + l2_cache: cache-controller at a000000 {
> + compatible = "metanoia,mt2824-ax45mp-cache",
> + "andestech,ax45mp-cache", "cache";
> + reg = <0x0 0x0a000000 0x0 0x40000>;
> + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
> + cache-line-size = <64>;
> + cache-level = <2>;
> + cache-sets = <1024>;
> + cache-size = <0x40000>;
> + cache-unified;
> + };
> +
> + plic: interrupt-controller at c000000 {
> + compatible = "metanoia,mt2824-plic", "andestech,nceplic100";
> + reg = <0x0 0x0c000000 0x0 0x400000>;
> + interrupts-extended = <&cpu0intc 0x0b>, <&cpu0intc 0x09>,
> + <&cpu1intc 0x0b>, <&cpu1intc 0x09>;
> + interrupt-controller;
> + #address-cells = <0x00>;
> + #interrupt-cells = <0x02>;
> + riscv,ndev = <0x47>;
> + };
> +
> + plmt: timer at c400000 {
> + compatible = "metanoia,mt2824-plmt", "andestech,plmt0";
> + reg = <0x0 0x0c400000 0x0 0x00400000>;
> + interrupts-extended = <&cpu0intc 0x07>,
> + <&cpu1intc 0x07>;
> + };
> +
> + plicsw: interrupt-controller at c800000 {
> + compatible = "metanoia,mt2824-plicsw", "andestech,plicsw";
> + reg = <0x0 0x0c800000 0x0 0x400000>;
> + interrupts-extended = <&cpu0intc 0x03>,
> + <&cpu1intc 0x03>;
> + };
> +
> + reboot: reboot at 10000004 {
> + compatible = "metanoia,mt2824-reboot";
> + reg = <0x0 0x10000004 0x0 0x08>;
> + };
> +
> + rst: reset-controller at 1000000c {
> + #reset-cells = <1>;
> + compatible = "metanoia,mt2824-reset";
> + reg = <0x0 0x1000000c 0x0 0x04>;
> + };
As pointed out, these are probably part of a syscon that I would imagine
also includes some clocks or other features.
By and large I think this is fine though..
Thanks,
Conor.
> +
> + watchdog: watchdog at 10090000 {
> + compatible = "metanoia,mt2824-wdt", "andestech,ae350-wdt";
> + reg = <0x0 0x10090000 0x0 0x10000>;
> + clocks = <&ext_clk>;
> + andestech,clock-source = <0>;
> + timeout-sec = <10>;
> + status = "disabled";
> + };
> +
> + serial0: serial at 100e0000 {
> + compatible = "ns16550a";
> + reg = <0x0 0x100e0000 0x0 0x1000>;
> + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&pclk_div4>;
> + current-speed = <115200>;
> + reg-shift = <0x02>;
> + reg-offset = <0x20>;
> + reg-io-width = <0x04>;
> + no-loopback-test;
> + status = "disabled";
> + };
> +
> + serial1: serial at 100f0000 {
> + compatible = "ns16550a";
> + reg = <0x0 0x100f0000 0x0 0x1000>;
> + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&pclk_div4>;
> + current-speed = <115200>;
> + reg-shift = <0x02>;
> + reg-offset = <0x20>;
> + reg-io-width = <0x04>;
> + no-loopback-test;
> + status = "disabled";
> + };
> +
> + qspi: spi at 10120000 {
> + compatible = "metanoia,mt2824-spi", "andestech,ae350-spi";
> + reg = <0x0 0x10120000 0x0 0x10000>;
> + interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <0x01>;
> + #size-cells = <0x00>;
> + num-cs = <0x01>;
> + clocks = <&pll_soc_out3>;
> + status = "disabled";
> + };
> +
> + spi0: spi at 10130000 {
> + compatible = "metanoia,mt2824-spi", "andestech,ae350-spi";
> + reg = <0x0 0x10130000 0x0 0x10000>;
> + #address-cells = <0x01>;
> + #size-cells = <0x00>;
> + num-cs = <0x01>;
> + clocks = <&pll_soc_out3>;
> + status = "disabled";
> + };
> +
> + spi1: spi at 10140000 {
> + compatible = "metanoia,mt2824-spi", "andestech,ae350-spi";
> + reg = <0x0 0x10140000 0x0 0x10000>;
> + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <0x01>;
> + #size-cells = <0x00>;
> + num-cs = <0x01>;
> + clocks = <&pll_soc_out3>;
> + status = "disabled";
> + };
> +
> + spi2: spi at 10150000 {
> + compatible = "metanoia,mt2824-spi", "andestech,ae350-spi";
> + reg = <0x0 0x10150000 0x0 0x10000>;
> + #address-cells = <0x01>;
> + #size-cells = <0x00>;
> + num-cs = <0x01>;
> + clocks = <&pll_soc_out3>;
> + status = "disabled";
> + };
> +
> + spi3: spi at 10160000 {
> + compatible = "metanoia,mt2824-spi", "andestech,ae350-spi";
> + reg = <0x0 0x10160000 0x0 0x10000>;
> + #address-cells = <0x01>;
> + #size-cells = <0x00>;
> + num-cs = <0x01>;
> + clocks = <&pll_soc_out3>;
> + status = "disabled";
> + };
> +
> + spi4: spi at 10170000 {
> + compatible = "metanoia,mt2824-spi", "andestech,ae350-spi";
> + reg = <0x0 0x10170000 0x0 0x10000>;
> + #address-cells = <0x01>;
> + #size-cells = <0x00>;
> + num-cs = <0x01>;
> + clocks = <&pll_soc_out3>;
> + status = "disabled";
> + };
> +
> + spi5: spi at 10180000 {
> + compatible = "metanoia,mt2824-spi", "andestech,ae350-spi";
> + reg = <0x0 0x10180000 0x0 0x10000>;
> + #address-cells = <0x01>;
> + #size-cells = <0x00>;
> + num-cs = <0x01>;
> + clocks = <&pll_soc_out3>;
> + status = "disabled";
> + };
> +
> + spi6: spi at 10190000 {
> + compatible = "metanoia,mt2824-spi", "andestech,ae350-spi";
> + reg = <0x0 0x10190000 0x0 0x10000>;
> + #address-cells = <0x01>;
> + #size-cells = <0x00>;
> + num-cs = <0x01>;
> + clocks = <&pll_soc_out3>;
> + status = "disabled";
> + };
> +
> + spi7: spi at 101a0000 {
> + compatible = "metanoia,mt2824-spi", "andestech,ae350-spi";
> + reg = <0x0 0x101a0000 0x0 0x10000>;
> + #address-cells = <0x01>;
> + #size-cells = <0x00>;
> + num-cs = <0x01>;
> + clocks = <&pll_soc_out3>;
> + status = "disabled";
> + };
> + };
> +
> + usb2phy: usb2-phy {
> + compatible = "metanoia,mt2824-usb2-phy";
> + #phy-cells = <0>;
> + resets = <&rst 18>;
> + reset-names = "usb2-phy";
> + };
> +
> + reserved-memory {
> + #address-cells = <0x2>;
> + #size-cells = <0x2>;
> + ranges;
> +
> + /* for the DSPs, configured as non-cacheable in openSBI */
> + rsc_table: rsc-table at 81000000 {
> + reg = <0x0 0x81000000 0x0 0x10000>;
> + no-map;
> + };
> + };
> +};
> diff --git a/arch/riscv/boot/dts/metanoia/mt5824-evb.dts b/arch/riscv/boot/dts/metanoia/mt5824-evb.dts
> new file mode 100644
> index 000000000000..d0e8eb0a49a4
> --- /dev/null
> +++ b/arch/riscv/boot/dts/metanoia/mt5824-evb.dts
> @@ -0,0 +1,81 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2026 Metanoia Communications Inc.. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "mt2824.dtsi"
> +
> +/ {
> + model = "Metanoia MT5824 EVB";
> + compatible = "metanoia,mt5824-evb", "metanoia,mt2824";
> +
> + aliases {
> + uart0 = &serial0;
> + uart1 = &serial1;
> + spi0 = &spi0;
> + spi1 = &spi1;
> + spi2 = &spi2;
> + };
> +
> + chosen {
> + stdout-path = "uart0:115200n8";
> + };
> +
> + memory at 80000000 {
> + device_type = "memory";
> + reg = <0x0 0x80000000 0x0 0x80000000>,
> + <0x1 0x00000000 0x0 0x80000000>;
> + };
> +};
> +
> +&usb0 {
> + status = "okay";
> +};
> +
> +&mmcsd {
> + bus-width = <8>;
> + mmc-ddr-1_8v;
> + mmc-hs200-1_8v;
> + mmc-hs400-1_8v;
> + no-sdio;
> + disable-wp;
> + cap-mmc-hw-reset;
> + status = "okay";
> +};
> +
> +&watchdog {
> + status = "okay";
> +};
> +
> +&serial0 {
> + status = "okay";
> +};
> +
> +&serial1 {
> + status = "okay";
> +};
> +
> +&qspi {
> + status = "okay";
> + flash at 0 {
> + compatible = "jedec,spi-nor";
> + spi-rx-bus-width = <0x4>;
> + spi-tx-bus-width = <0x4>;
> + spi-max-frequency = <100000000>;
> + reg = <0x0>;
> + };
> +};
> +
> +&spi0 {
> + status = "okay";
> +};
> +
> +&spi1 {
> + status = "okay";
> +};
> +
> +&spi2 {
> + status = "okay";
> +};
>
> --
> 2.56.0
>
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