[PATCH 24/25] riscv: add Metanoia MT2824 SoC and MT5824 EVB support
Krzysztof Kozlowski
krzk at kernel.org
Fri Nov 6 03:21:41 PST 2026
On 06/11/2026 10:30, Benoît Monin wrote:
> Add the device tree for the Metanoia MT2824, a dual-core Andes
> AX45MP-based SoC, and for the MT5824 evaluation board.
>
> The SoC device tree describes the CPUs and their L2 cache, the PLIC,
> PLICSW and PLMT, the reset controller, the reboot controller, the
> watchdog, two UARTs, the QSPI and eight SPI controllers, the DWC
> MSHC MMC controller, and the USB2 controller.
>
> The MT5824 EVB enables the watchdog, the two UARTs, the MMC
> controller, the QSPI port with its SPI-NOR flash, the first three SPI
> controllers, and the USB controller.
>
> Originally-by: Jun Chang <jun.chang at metanoia-comm.com>
> Signed-off-by: Benoît Monin <benoit.monin at bootlin.com>
> ---
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/metanoia/Makefile | 2 +
> arch/riscv/boot/dts/metanoia/mt2824.dtsi | 330 ++++++++++++++++++++++++++++
> arch/riscv/boot/dts/metanoia/mt5824-evb.dts | 81 +++++++
> 4 files changed, 414 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index 69d8751fb17c..8e1e987ea089 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -4,6 +4,7 @@ subdir-y += andes
> subdir-y += anlogic
> subdir-y += canaan
> subdir-y += eswin
> +subdir-y += metanoia
> subdir-y += microchip
> subdir-y += renesas
> subdir-y += sifive
> diff --git a/arch/riscv/boot/dts/metanoia/Makefile b/arch/riscv/boot/dts/metanoia/Makefile
> new file mode 100644
> index 000000000000..7a685798d5a4
> --- /dev/null
> +++ b/arch/riscv/boot/dts/metanoia/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_METANOIA) += mt5824-evb.dtb
> diff --git a/arch/riscv/boot/dts/metanoia/mt2824.dtsi b/arch/riscv/boot/dts/metanoia/mt2824.dtsi
> new file mode 100644
> index 000000000000..5f73c6d3760b
> --- /dev/null
> +++ b/arch/riscv/boot/dts/metanoia/mt2824.dtsi
> @@ -0,0 +1,330 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2026 Metanoia Communications Inc.. All rights reserved.
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + #address-cells = <0x02>;
> + #size-cells = <0x02>;
> + compatible = "metanoia,mt2824";
> +
> + cpus: cpus {
> + #address-cells = <0x01>;
> + #size-cells = <0x00>;
> + timebase-frequency = <20000000>;
> +
> + cpu0: cpu at 0 {
> + device_type = "cpu";
> + reg = <0x00>;
> + compatible = "andestech,ax45mp", "riscv";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> + "zicntr", "zicsr", "zifencei",
> + "zihpm", "xandespmu";
> + mmu-type = "riscv,sv39";
> + clock-frequency = <900000000>;
> + i-cache-size = <0x8000>;
> + i-cache-sets = <0x100>;
> + i-cache-line-size = <0x40>;
> + i-cache-block-size = <0x40>;
> + d-cache-size = <0x8000>;
> + d-cache-sets = <0x80>;
> + d-cache-line-size = <0x40>;
> + d-cache-block-size = <0x40>;
> + next-level-cache = <&l2_cache>;
> +
> + cpu0intc: interrupt-controller {
> + #interrupt-cells = <0x01>;
> + interrupt-controller;
> + compatible = "andestech,cpu-intc", "riscv,cpu-intc";
> + };
> + };
> +
> + cpu1: cpu at 1 {
> + device_type = "cpu";
> + reg = <0x01>;
> + compatible = "andestech,ax45mp", "riscv";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> + "zicntr", "zicsr", "zifencei",
> + "zihpm", "xandespmu";
> + mmu-type = "riscv,sv39";
> + clock-frequency = <900000000>;
> + i-cache-size = <0x8000>;
> + i-cache-sets = <0x100>;
> + i-cache-line-size = <0x40>;
> + i-cache-block-size = <0x40>;
> + d-cache-size = <0x8000>;
> + d-cache-sets = <0x80>;
> + d-cache-line-size = <0x40>;
> + d-cache-block-size = <0x40>;
> + next-level-cache = <&l2_cache>;
> +
> + cpu1intc: interrupt-controller {
> + #interrupt-cells = <0x01>;
> + interrupt-controller;
> + compatible = "andestech,cpu-intc", "riscv,cpu-intc";
> + };
> + };
> + };
> +
> + clocks {
> + ext_clk: ext-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <20000000>;
> + clock-output-names = "ext-clk";
> + };
> +
> + pclk_div4: platform-clock-div4 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <225000000>;
> + clock-output-names = "platform-clock-div4";
> + };
> +
> + pll_soc_out3: pll-soc-out3 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <180000000>;
> + clock-output-names = "pll-soc-out3";
> + };
> +
> + usb_otg_ahb_clk: clock-usb-otg-ahb {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <60000000>;
> + clock-output-names = "otg";
> + };
> + };
> +
> + soc: soc {
> + #address-cells = <0x02>;
> + #size-cells = <0x02>;
> + compatible = "simple-bus";
> + interrupt-parent = <&plic>;
> + ranges;
> +
> + usb0: usb at 4000000 {
> + compatible = "metanoia,mt2824-usb", "snps,dwc2";
> + reg = <0x0 0x04000000 0x0 0x100000>;
> + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&usb_otg_ahb_clk>;
> + clock-names = "otg";
> + dr_mode = "host";
> + resets = <&rst 19>, <&rst 20>;
> + reset-names = "dwc2", "dwc2-ecc";
> + phys = <&usb2phy>;
> + phy-names = "usb2-phy";
> + hnp-disable;
> + srp-disable;
> + disable-over-current;
> + status = "disabled";
> + };
> +
> + mmcsd: mmc at 4100000 {
> + compatible = "metanoia,mt2824-dwcmshc";
> + clocks = <&pll_soc_out3>;
> + clock-names = "core";
> + reg = <0x0 0x04100000 0x0 0x00100000>;
Please follow coding style and dt-checkstyle.
Also 0x00100000 is 0x100000
Anywya, look at size of address space. 0x100000, right?
...
> + reboot: reboot at 10000004 {
> + compatible = "metanoia,mt2824-reboot";
> + reg = <0x0 0x10000004 0x0 0x08>;
Now look here - 0x8
> + };
> +
> + rst: reset-controller at 1000000c {
> + #reset-cells = <1>;
Random coding style.
> + compatible = "metanoia,mt2824-reset";
> + reg = <0x0 0x1000000c 0x0 0x04>;
and 0x4.
Do you see the problem?
Why do you pad some numbers?
> + };
> +
> + watchdog: watchdog at 10090000 {
> + compatible = "metanoia,mt2824-wdt", "andestech,ae350-wdt";
> + reg = <0x0 0x10090000 0x0 0x10000>;
> + clocks = <&ext_clk>;
> + andestech,clock-source = <0>;
> + timeout-sec = <10>;
> + status = "disabled";
Why? It's always there, no?
> +
> + usb2phy: usb2-phy {
Follow DTS coding style.
Best regards,
Krzysztof
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