[PATCH v1 4/4] MAINTAINERS: degrade RISC-V MISC SOC SUPPORT to Odd Fixes

[Conor Dooley]

From: Conor Dooley <conor.dooley at microchip.com>

The SiFive and Canaan platforms are not being actively looked after at
this point, but fixes for them would be applied if/when the patches
appeared. Since they're now the only things in the RISC-V MISC SOC
SUPPORT, mark them as Odd Fixes. I don't believe this is a functional
change, it just represents what's actually happening - particularly
since the Canaan k230 never built up enough steam to get merged and the
new SiFive demo chips have been done in partnership with with other
companies, e.g. Eswin, and will reside in their directories instead.

Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index e5e4bcf7a408..735f5447c52d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -22117,7 +22117,7 @@ F:	include/soc/microchip/mpfs.h
 RISC-V MISC SOC SUPPORT
 M:	Conor Dooley <conor at kernel.org>
 L:	linux-riscv at lists.infradead.org
-S:	Maintained
+S:	Odd Fixes
 T:	git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
 F:	arch/riscv/boot/dts/canaan/
 F:	arch/riscv/boot/dts/sifive/
-- 
2.51.0