[PATCH v1 4/4] MAINTAINERS: degrade RISC-V MISC SOC SUPPORT to Odd Fixes

[Paul Walmsley]

On Sun, 23 Nov 2025, Conor Dooley wrote:

> From: Conor Dooley <conor.dooley at microchip.com>
> 
> The SiFive and Canaan platforms are not being actively looked after at
> this point, but fixes for them would be applied if/when the patches
> appeared. Since they're now the only things in the RISC-V MISC SOC
> SUPPORT, mark them as Odd Fixes. I don't believe this is a functional
> change, it just represents what's actually happening - particularly
> since the Canaan k230 never built up enough steam to get merged and the
> new SiFive demo chips have been done in partnership with with other
> companies, e.g. Eswin, and will reside in their directories instead.
> 
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>

Reviewed-by: Paul Walmsley <pjw at kernel.org>

- Paul