[PATCH v1 3/4] MAINTAINERS: add tree to RISC-V Microchip entry

[Conor Dooley]

From: Conor Dooley <conor.dooley at microchip.com>

In fairness to my own employer, lumping it in as "misc" is not quite
accurate when they do pay me to look after the platform. Move the tree
link for it to its entry, rather than having the RISC-V MISC SOC SUPPORT
entry cover it.

Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 0836b5422826..e5e4bcf7a408 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -22084,6 +22084,7 @@ M:	Conor Dooley <conor.dooley at microchip.com>
 M:	Daire McNamara <daire.mcnamara at microchip.com>
 L:	linux-riscv at lists.infradead.org
 S:	Supported
+T:	git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ (dts, soc, firmware)
 F:	Documentation/devicetree/bindings/clock/microchip,mpfs*.yaml
 F:	Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
 F:	Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml
@@ -22119,7 +22120,6 @@ L:	linux-riscv at lists.infradead.org
 S:	Maintained
 T:	git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
 F:	arch/riscv/boot/dts/canaan/
-F:	arch/riscv/boot/dts/microchip/
 F:	arch/riscv/boot/dts/sifive/
 
 RISC-V PMU DRIVERS
-- 
2.51.0