[PATCH 2/5] riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property
Prabhakar
prabhakar.csengg at gmail.com
Thu Sep 28 17:07:01 PDT 2023
From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
RZ/Five is a noncoherent SoC so to indicate this add dma-noncoherent
property to RZ/Five SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
---
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index c8d63a8f7d86..b0796015e36b 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -43,6 +43,7 @@ cpu0_intc: interrupt-controller {
};
&soc {
+ dma-noncoherent;
interrupt-parent = <&plic>;
plic: interrupt-controller at 12c00000 {
--
2.34.1
More information about the linux-riscv
mailing list