[PATCH 1/5] riscv: dts: renesas: r9a07g043f: Add L2 cache node
Prabhakar
prabhakar.csengg at gmail.com
Thu Sep 28 17:07:00 PDT 2023
From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
Add L2 cache node for RZ/Five SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
---
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index 6ec1c6f9a403..c8d63a8f7d86 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -29,6 +29,7 @@ cpu0: cpu at 0 {
i-cache-line-size = <0x40>;
d-cache-size = <0x8000>;
d-cache-line-size = <0x40>;
+ next-level-cache = <&l2cache>;
clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
operating-points-v2 = <&cluster0_opp>;
@@ -56,4 +57,15 @@ plic: interrupt-controller at 12c00000 {
resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
};
+
+ l2cache: cache-controller at 13400000 {
+ compatible = "andestech,ax45mp-cache", "cache";
+ reg = <0x0 0x13400000 0x0 0x100000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(476) IRQ_TYPE_LEVEL_HIGH>;
+ cache-size = <0x40000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-unified;
+ cache-level = <2>;
+ };
};
--
2.34.1
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