[PATCH 07/10] arm64: dts: realtek: rtd129x-usb: Add rtd129x usb module nodes
stanley_chang
stanley_chang at realtek.com
Thu Sep 17 04:38:32 EDT 2020
Signed-off-by: stanley_chang <stanley_chang at realtek.com>
---
arch/arm64/boot/dts/realtek/rtd129x-usb.dtsi | 203 +++++++++++++++++++
1 file changed, 203 insertions(+)
create mode 100644 arch/arm64/boot/dts/realtek/rtd129x-usb.dtsi
diff --git a/arch/arm64/boot/dts/realtek/rtd129x-usb.dtsi b/arch/arm64/boot/dts/realtek/rtd129x-usb.dtsi
new file mode 100644
index 000000000000..82537da8f4fb
--- /dev/null
+++ b/arch/arm64/boot/dts/realtek/rtd129x-usb.dtsi
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+/*
+ * Realtek RTD129x SoC USB
+ *
+ * Copyright (c) 2020 Realtek Semiconductor Corp.
+ */
+
+/ {
+ dwc3_drd_usb3phy: dwc3_drd_usb3phy at 98013210 {
+ compatible = "realtek,usb3phy";
+ reg = <0x98013210 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ phyN = <1>;
+ phy0 {
+ phy_data_size = <0x30>;
+ phy_data_addr = /bits/ 8
+ <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09
+ 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13
+ 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D
+ 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27
+ 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F>;
+ phy_data_revA = /bits/ 16
+ <0x4008 0xE046 0x6046 0x2779 0x72F5 0x2AD3 0x000E
+ 0x2E00 0x3591 0x525C 0xA600 0xA904 0xC000 0xEF1C
+ 0x2000 0x0000 0x000C 0x4C00 0xFC00 0x0C81 0xDE01
+ 0x0000 0x0000 0x0000 0x0000 0x4004 0x1260 0xFF00
+ 0xCB00 0xA03F 0xC2E0 0x2807 0x947A 0x88AA 0x0057
+ 0xAB66 0x0800 0x0000 0x040A 0x01D6 0xF8C2 0x3080
+ 0x3082 0x2078 0xFFFF 0xFFFF 0x0000 0x0040>;
+ do_toggle;
+ };
+ };
+
+ dwc3_drd_usb2phy: dwc3_drd_usb2phy at 98013214 {
+ compatible = "realtek,usb2phy";
+ reg = <0x98013214 0x4>, <0x98028280 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ phyN = <1>;
+ phy0 {
+ phy_data_page0_size = <16>;
+ phy_data_page0_addr = /bits/ 8
+ <0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xF0 0xF1
+ 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7>;
+ phy_data_page0_data = /bits/ 8
+ <0x90 0x30 0x3A 0x8D 0xA8 0x65 0x91 0x81 0xFC 0x8C
+ 0x00 0x11 0x9B 0x81 0x00 0x02>;
+ phy_data_page1_size = <8>;
+ phy_data_page1_addr = /bits/ 8
+ <0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7>;
+ phy_data_page1_data = /bits/ 8
+ <0x25 0xEF 0x60 0x00 0x00 0x0F 0x18 0xE3>;
+ do_toggle;
+ //check_efuse;
+ };
+ };
+
+ dwc3_drd: rtk_dwc3_drd at 98013200 {
+ compatible = "realtek,dwc3";
+ reg = <0x98013200 0x200>;
+ interrupts = <0 21 4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ delay_probe_work; //To delay probe work
+
+ dwc3_drd at 98020000 {
+ compatible = "synopsys,dwc3";
+ reg = <0x98020000 0x9000>;
+ interrupts = <0 21 4>;
+ snps,fixed_dwc3_globals_regs_start = <0x8100>;
+ usb-phy = <&dwc3_drd_usb2phy &dwc3_drd_usb3phy>;
+ dr_mode = "host"; /*otg, host, peripheral*/
+ snps,dis_u2_susphy_quirk; // Add workaround for Usb3.0 hub suspend
+ snps,parkmode-disable-ss-quirk; // disable usb3.0 park mode
+ };
+ };
+
+ dwc3_u2host_usb2phy: dwc3_u2host_usb2phy at 98013C14 {
+ compatible = "realtek,usb2phy";
+ reg = <0x98013C14 0x4>, <0x98031280 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ phyN = <1>;
+ phy0 {
+ phy_data_page0_size = <16>;
+ phy_data_page0_addr = /bits/ 8
+ <0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xF0 0xF1
+ 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7>;
+ phy_data_page0_data = /bits/ 8
+ <0x90 0x30 0x3A 0x8D 0xA6 0x65 0x91 0x81 0xFC 0x8C
+ 0x00 0x11 0x9B 0x81 0x00 0x02>;
+ phy_data_page1_size = <8>;
+ phy_data_page1_addr = /bits/ 8
+ <0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7>;
+ phy_data_page1_data = /bits/ 8
+ <0x25 0xEF 0x60 0x00 0x00 0x0F 0x18 0xE3>;
+ do_toggle;
+ //check_efuse;
+ };
+ };
+
+ dwc3_u2host: rtk_dwc3_u2host at 98013E00 {
+ compatible = "realtek,dwc3";
+ reg = <0x98013C00 0x200>;
+ interrupts = <0 21 4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ delay_probe_work; //To delay probe work
+
+ dwc3_u2host at 98029000 {
+ compatible = "synopsys,dwc3";
+ reg = <0x98029000 0x9000>;
+ interrupts = <0 21 4>;
+ snps,fixed_dwc3_globals_regs_start = <0x8100>;
+ usb-phy = <&dwc3_u2host_usb2phy>;
+ dr_mode = "host"; /*only host*/
+ snps,dis_u2_susphy_quirk; // Add workaround for Usb3.0 hub suspend
+ };
+ };
+
+ dwc3_u3host_usb3phy: dwc3_u3host_usb3phy at 98013E10 {
+ compatible = "realtek,usb3phy";
+ reg = <0x98013E10 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disable";
+ phyN = <1>;
+ phy0 {
+ phy_data_size = <0x30>;
+ phy_data_addr = /bits/ 8
+ <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09
+ 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13
+ 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D
+ 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27
+ 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F>;
+ phy_data_revA = /bits/ 16
+ <0x4008 0xE046 0x6046 0x2779 0x72F5 0x2AD3 0x000E
+ 0x2E00 0x3591 0x525C 0xA600 0xA904 0xC000 0xEF1C
+ 0x2000 0x0000 0x000C 0x4C00 0xFC00 0x0C81 0xDE01
+ 0x0000 0x0000 0x0000 0x0000 0x4004 0x1260 0xFF00
+ 0xCB00 0xA03F 0xC2E0 0x2807 0x9424 0x284A 0x0057
+ 0xAB66 0x0800 0x0000 0x040A 0x01D6 0xF8C2 0x3080
+ 0x3082 0x2078 0xFFFF 0xFFFF 0x0000 0x0040>;
+ do_toggle;
+ };
+ };
+
+ dwc3_u3host_usb2phy: dwc3_u3host_usb2phy at 98013E14 {
+ compatible = "realtek,usb2phy";
+ reg = <0x98013E14 0x4>, <0x981F8280 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disable";
+ phyN = <1>;
+ phy0 {
+ phy_data_page0_size = <16>;
+ phy_data_page0_addr = /bits/ 8
+ <0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xF0 0xF1
+ 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7>;
+ phy_data_page0_data = /bits/ 8
+ <0x90 0x30 0x3A 0x8D 0xA6 0x65 0x91 0x81 0xFC 0x8C
+ 0x00 0x11 0x9B 0x81 0x00 0x02>;
+ phy_data_page1_size = <8>;
+ phy_data_page1_addr = /bits/ 8
+ <0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7>;
+ phy_data_page1_data = /bits/ 8
+ <0x25 0xEF 0x60 0x00 0x00 0x0F 0x18 0xE3>;
+ do_toggle;
+ //check_efuse;
+ };
+ };
+
+ dwc3_u3host: rtk_dwc3_u3host at 98013E00 {
+ compatible = "realtek,dwc3";
+ reg = <0x98013E00 0x200>;
+ interrupts = <0 21 4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ delay_probe_work; //To delay probe work
+
+ status = "disable";
+
+ dwc3_u3host at 981F0000 {
+ compatible = "synopsys,dwc3";
+ reg = <0x981F0000 0x9000>;
+ interrupts = <0 21 4>;
+ snps,fixed_dwc3_globals_regs_start = <0x8100>;
+ usb-phy = <&dwc3_u3host_usb2phy &dwc3_u3host_usb3phy>;
+ dr_mode = "host"; /*only host*/
+ snps,dis_u2_susphy_quirk; // Add workaround for Usb3.0 hub suspend
+ snps,parkmode-disable-ss-quirk; // disable usb3.0 park mode
+ };
+ };
+};
--
2.28.0
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