[PATCH 08/10] arm64: dts: realtek: rtd139x-usb: Add rtd139x usb module nodes

[stanley_chang]

Signed-off-by: stanley_chang <stanley_chang at realtek.com>
---
 arch/arm64/boot/dts/realtek/rtd139x-usb.dtsi | 120 +++++++++++++++++++
 1 file changed, 120 insertions(+)
 create mode 100644 arch/arm64/boot/dts/realtek/rtd139x-usb.dtsi

diff --git a/arch/arm64/boot/dts/realtek/rtd139x-usb.dtsi b/arch/arm64/boot/dts/realtek/rtd139x-usb.dtsi
new file mode 100644
index 000000000000..a98cf134aa52
--- /dev/null
+++ b/arch/arm64/boot/dts/realtek/rtd139x-usb.dtsi
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+/*
+ * Realtek RTD139x SoC USB
+ *
+ * Copyright (c) 2020 Realtek Semiconductor Corp.
+ */
+
+/ {
+	dwc3_drd_usb2phy: dwc3_drd_usb2phy at 98013214 {
+		compatible = "realtek,usb2phy";
+		reg = <0x98013214 0x4>, <0x98028280 0x4>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		phyN = <1>;
+		phy0 {
+			phy_data_page0_size = <16>;
+			phy_data_page0_addr = /bits/ 8
+				<0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xF0 0xF1
+				0xF2 0xF3 0xF4 0xF5 0xF6 0xF7>;
+			phy_data_page0_data = /bits/ 8
+				<0xE0 0x30 0x79 0x8D 0xAC 0x65 0x01 0x81 0xFC 0x8C
+				0x00 0x11 0x9B 0x00 0x00 0x02>;
+			phy_data_page1_size = <8>;
+			phy_data_page1_addr = /bits/ 8
+				<0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7>;
+			phy_data_page1_data = /bits/ 8
+				<0x25 0xEF 0x60 0x00 0x00 0x0F 0x18 0xE3>;
+			do_toggle;
+			check_efuse;
+			//use_default_parameter;
+		};
+	};
+
+	dwc3_drd: rtk_dwc3_drd at 98013200 {
+		compatible = "realtek,dwc3";
+		reg = <0x98013200 0x200>;
+		interrupts = <0 21 4>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		delay_probe_work; //To delay probe work
+		status = "okay";
+
+		dwc3_drd at 98020000 {
+			compatible = "synopsys,dwc3";
+			reg = <0x98020000 0x9000>;
+			interrupts = <0 21 4>;
+			snps,fixed_dwc3_globals_regs_start = <0x8100>;
+			usb-phy = <&dwc3_drd_usb2phy>;
+			dr_mode = "host"; /*otg, host, peripheral*/
+			snps,dis_u2_susphy_quirk; // Add workaround for Usb3.0 hub suspend
+		};
+	};
+
+	dwc3_u2host_usb2phy: dwc3_u2host_usb2phy at 98013C14 {
+		compatible = "realtek,usb2phy";
+		reg = <0x98013C14 0x4>, <0x98031280 0x4>, <0x98031284 0x4>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		phyN = <2>;
+		phy0 {
+			phy_data_page0_size = <16>;
+			phy_data_page0_addr = /bits/ 8
+				<0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xF0 0xF1
+				0xF2 0xF3 0xF4 0xF5 0xF6 0xF7>;
+			phy_data_page0_data = /bits/ 8
+				<0xE0 0x30 0x79 0x8D 0xAC 0x65 0x01 0x81 0xFC 0x8C
+				0x00 0x11 0x9B 0x00 0x00 0x02>;
+			phy_data_page1_size = <8>;
+			phy_data_page1_addr = /bits/ 8
+				<0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7>;
+			phy_data_page1_data = /bits/ 8
+				<0x25 0xEF 0x60 0x00 0x00 0x0F 0x18 0xE3>;
+			do_toggle;
+			check_efuse;
+			//use_default_parameter;
+		};
+		phy1 {
+			phy_data_page0_size = <16>;
+			phy_data_page0_addr = /bits/ 8
+				<0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xF0 0xF1
+				0xF2 0xF3 0xF4 0xF5 0xF6 0xF7>;
+			phy_data_page0_data = /bits/ 8
+				<0xE0 0x30 0x79 0x8D 0xAC 0x65 0x01 0x81 0xFC 0x8C
+				0x00 0x11 0x9B 0x00 0x00 0x02>;
+			phy_data_page1_size = <8>;
+			phy_data_page1_addr = /bits/ 8
+				<0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7>;
+			phy_data_page1_data = /bits/ 8
+				<0x25 0xEF 0x60 0x00 0x00 0x0F 0x18 0xE3>;
+			do_toggle;
+			check_efuse;
+			//use_default_parameter;
+		};
+	};
+
+	dwc3_u2host: rtk_dwc3_u2host at 98013E00 {
+		compatible = "realtek,dwc3";
+		reg = <0x98013C00 0x200>;
+		interrupts = <0 21 4>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		delay_probe_work; //To delay probe work
+		status = "okay";
+
+		dwc3_u2host at 98029000 {
+			compatible = "synopsys,dwc3";
+			reg = <0x98029000 0x9000>;
+			interrupts = <0 21 4>;
+			snps,fixed_dwc3_globals_regs_start = <0x8100>;
+			usb-phy = <&dwc3_u2host_usb2phy>;
+			dr_mode = "host"; /*only host*/
+			snps,dis_u2_susphy_quirk; // Add workaround for Usb3.0 hub suspend
+		};
+	};
+
+};
-- 
2.28.0