[PATCH 06/10] doc: dt: bindings: phy: rtk: Add the doc about new rtk usb phy driver

[stanley_chang]

Two documentations explain the property about realtek USB2 and USB3 phy drivers.

Signed-off-by: stanley_chang <stanley_chang at realtek.com>
---
 .../devicetree/bindings/phy/phy-rtk-usb2.yaml | 73 ++++++++++++++++++
 .../devicetree/bindings/phy/phy-rtk-usb3.yaml | 76 +++++++++++++++++++
 2 files changed, 149 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-rtk-usb2.yaml
 create mode 100644 Documentation/devicetree/bindings/phy/phy-rtk-usb3.yaml

diff --git a/Documentation/devicetree/bindings/phy/phy-rtk-usb2.yaml b/Documentation/devicetree/bindings/phy/phy-rtk-usb2.yaml
new file mode 100644
index 000000000000..49382c9587b2
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-rtk-usb2.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2020 Realtek Semiconductor Corporation
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/phy-rtk-usb2.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Realtek DHC SoCs USB2 PHY
+
+maintainers:
+  - Stanley Chang <stanley_chang at realtek.com>
+
+properties:
+  compatible:
+    enum:
+      - realtek,usb2phy
+
+  reg:
+    maxItems: 2
+
+  phyN:
+    description:
+        The number of USB 2.0 PHY  in controller.
+
+  phy0:
+     description:
+       The node of PHY parameter.
+
+required:
+  - compatible
+  - reg
+  - phyN
+  - phy0
+
+examples:
+  - |
+    dwc3_u3drd_usb2phy: dwc3_u3drd_usb2phy at 98013E14 {
+        compatible = "realtek,usb2phy";
+        reg = <0x98013E14 0x4>, <0x98058280 0x4>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+        status = "okay";
+        phyN = <1>;
+
+        phy0 {
+            phy_data_page0_size = <16>;
+            phy_data_page0_addr = /bits/ 8
+                <0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xF0 0xF1
+                0xF2 0xF3 0xF4 0xF5 0xF6 0xF7>;
+            phy_data_page0_A00 = /bits/ 8
+                <0xE0 0x30 0x79 0x8D 0x6A 0x65 0x01 0x71 0xFC 0x8C
+                0x00 0x11 0x9B 0x00 0x00 0x0A>;
+            phy_data_page0_B00 = /bits/ 8
+                <0x18 0x30 0x79 0x8D 0x6A 0x65 0x01 0x71 0xFC 0x8C
+                0x00 0x11 0x9B 0x00 0x00 0x32>;
+            phy_data_page1_size = <8>;
+            phy_data_page1_addr = /bits/ 8
+                <0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7>;
+            phy_data_page1_A00 = /bits/ 8
+                <0x25 0xEF 0x60 0x44 0x00 0x0F 0x18 0xE3>;
+            phy_data_page2_size = <1>;
+            phy_data_page2_addr = /bits/ 8
+                <0xE0>;
+            phy_data_page2_A00 = /bits/ 8
+                <0x01>;
+            do_toggle;
+            check_efuse;
+            //use_default_parameter;
+            is_double_sensitivity_mode;
+            ldo_page0_e4_compensate = <(-2)>;
+        };
+    };
diff --git a/Documentation/devicetree/bindings/phy/phy-rtk-usb3.yaml b/Documentation/devicetree/bindings/phy/phy-rtk-usb3.yaml
new file mode 100644
index 000000000000..3ff6449b5d2f
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-rtk-usb3.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2020 Realtek Semiconductor Corporation
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/phy-rtk-usb2.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Realtek DHC SoCs USB3 PHY
+
+maintainers:
+  - Stanley Chang <stanley_chang at realtek.com>
+
+properties:
+  compatible:
+    enum:
+      - realtek,usb3phy
+
+  reg:
+    maxItems: 1
+
+  phyN:
+    description:
+        The number of USB 3.0 PHY  in controller.
+
+  phy0:
+     description:
+       The node of PHY parameter.
+
+required:
+  - compatible
+  - reg
+  - phyN
+  - phy0
+
+examples:
+  - |
+    dwc3_u3drd_usb3phy: dwc3_u3drd_usb3phy at 98013E10 {
+        compatible = "realtek,usb3phy";
+        reg = <0x98013E10 0x4>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+        status = "okay";
+        port_index = <0>; /* index in u3 port */
+        phyN = <1>;
+
+        phy0 {
+            phy_data_size = <0x30>;
+            phy_data_addr = /bits/ 8
+                <0x00 0x01 0x02 0x03 0x04 0x05 0x06
+                0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D
+                0x0E 0x0F 0x10 0x11 0x12 0x13 0x14
+                0x15 0x16 0x17 0x18 0x19 0x1A 0x1B
+                0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22
+                0x23 0x24 0x25 0x26 0x27 0x28 0x29
+                0x2A 0x2B 0x2C 0x2D 0x2E 0x2F>;
+            phy_data_A00 = /bits/ 16
+                <0x400C 0xAC86 0x6042 0x2771 0x72F5 0x2AD3 0x0003
+                    0x2E00 0x3591 0x925C 0xA608 0xA905 0xC000 0xEF1E
+                    0x2010 0x8D50 0x000C 0x4C10 0xFC00 0x0C81 0xDE01
+                    0x0000 0x0000 0x0000 0x0000 0x6000 0x0085 0x2014
+                    0xC900 0xA03F 0xC2E0 0x7E00 0x705A 0xF645 0x0013
+                    0xCB66 0x4770 0x126C 0x840A 0x01D6 0xF802 0xff04
+                    0x3040 0x8028 0xFFFF 0xFFFF 0x0000 0x8600>;
+            phy_data_B00 = /bits/ 16
+                <0x400C 0xAC86 0x6042 0x2771 0x72F5 0x2AD3 0x0003
+                    0x2E00 0x3591 0x924C 0xA608 0xB905 0xC000 0xEF1E
+                    0x2010 0x8D50 0x000C 0x4C10 0xFC00 0x0C81 0xDE01
+                    0x0000 0x0000 0x0000 0x0000 0x6000 0x0085 0x2014
+                    0xC900 0xA03F 0xC2E0 0x7E00 0x705A 0xF645 0x0013
+                    0xCB66 0x4770 0x126C 0x840A 0x01D6 0xF802 0xff04
+                    0x3040 0x8028 0xFFFF 0xFFFF 0x0000 0x8600>;
+            do_toggle;
+            //use_default_parameter;
+        };
+    };
-- 
2.28.0