How does an SPI NOR handle a single byte write in Octal DTR mode?

[Takahiro Kuwano]

Hi Tudor,

In case of Infineon(Cypress) S28 devices, it can be done by de-asserting
chip select before clock falling (not sure typical controllers support this).
That means the device can take odd address in 8D-8D-8D mode.

Thanks,
Takahiro

On 12/20/2021 6:36 PM, Tudor.Ambarus at microchip.com wrote:
> Hello,
> 
> We're trying to understand how flashes handle single byte writes in
> Octal DTR mode, and since we haven't found this info in the datasheets
> that we read, you're our only hope. Can you shed some light and let us
> now:
> 1/  Do the flashes ignore the second byte in Octal DTR mode? Are we forced
> to first read the byte that we want to update together with the second byte,
> so that when writing in Octal DTR mode to write the 2nd byte that we've just
> read, so that we don't change its value?
> 2/ Can reads or writes start at an odd address in 8D-8D-8D mode? Pratyush
> proposed something at:
> https://patchwork.ozlabs.org/project/linux-mtd/list/?series=246518
> Are the assumptions correct in the patch set?
> 
> Feel free to forward this to anyone interested. Thanks.
> ta
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