How does an SPI NOR handle a single byte write in Octal DTR mode?

[Tudor.Ambarus at microchip.com]

Hello,

We're trying to understand how flashes handle single byte writes in
Octal DTR mode, and since we haven't found this info in the datasheets
that we read, you're our only hope. Can you shed some light and let us
now:
1/  Do the flashes ignore the second byte in Octal DTR mode? Are we forced
to first read the byte that we want to update together with the second byte,
so that when writing in Octal DTR mode to write the 2nd byte that we've just
read, so that we don't change its value?
2/ Can reads or writes start at an odd address in 8D-8D-8D mode? Pratyush
proposed something at:
https://patchwork.ozlabs.org/project/linux-mtd/list/?series=246518
Are the assumptions correct in the patch set?

Feel free to forward this to anyone interested. Thanks.
ta