How does an SPI NOR handle a single byte write in Octal DTR mode?

[Michael Walle]

Hi,

Am 2021-12-20 11:32, schrieb Takahiro Kuwano:
> In case of Infineon(Cypress) S28 devices, it can be done by 
> de-asserting
> chip select before clock falling (not sure typical controllers support 
> this).
> That means the device can take odd address in 8D-8D-8D mode.

Ahh nice. FWIW, I had a quick look at the FlexSPI controller found on
the NXP LS1028A, it doesn't seem to support deasserting the CS after
half a clock cycle, though.

-michael