[MLC NAND]: data pattern sensivity

Tue Apr 7 08:08:33 PDT 2015

On Tue, 07 Apr 2015 15:21:25 +0200
Andrea Scian <rnd4 at dave-tech.it> wrote:

> Thanks for linking this again.
> I think that Jeff can help us in understanding this further.
> The documents is pretty old (2009) and is about TLC only.
> Does it mean that MLC are less (or not at all) affected by this issue?

Some MLC chips require a randomization step: take a look at this
datasheet [1], page 21:
"Users are required to employ randomizer function in the NAND
controller to meet target endurance of the device."

[1]http://www.100y.com.tw/pdf_file/37-SAMSUNG-K9GBG08U0A-SCB0.pdf


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Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com