[MLC NAND]: data pattern sensivity

[Andrea Scian]

Il 07/04/2015 13:19, Boris Brezillon ha scritto:
> Hi,
> 
> On Tue, 07 Apr 2015 12:31:10 +0200
> Andrea Scian <rnd4 at dave-tech.it> wrote:
> 
>> Il 03/04/2015 19:20, Jeff Lauruhn (jlauruhn) ha scritto:
>>> I'm always glad to help out. I'm not sure I quite understand the meaning of "data pattern sensivity", but when I read it seem related to ECC code word size and Cyclicdesign.com is a good resource and in particular http://cyclicdesign.com/whitepapers/Cyclic_Design_NAND_ECC.pdf.  
>>
>> Thanks for pointing out the whitepaper
> 
> I haven't read this paper yet, but according to the title I doubt it is
> related to the "repeated/systematic data pattern" issue.
> 
>>
>>> If I'm off track let me know and I will keep looking.
>>
>> I don't really know, but, IIUC, is something related to NAND technology
>> and its impact is dependent from the specific MLC implementation.
>> For sure Boris can help us in have a better understanding of this issue :-)
> 
> Actually this problem was mentioned in the Micron document I pointed
> out in a previous thread ([1] page 14).

Thanks for linking this again.
I think that Jeff can help us in understanding this further.
The documents is pretty old (2009) and is about TLC only.
Does it mean that MLC are less (or not at all) affected by this issue?

> I also found a paper describing the benefit of data scrambling on MLC
> chips [2].

This one is really interesting, thanks.
IIUC, what they say is that data scrambling is always useful in NAND
flash to increase endurance (and also decrease RBER).
At the beginning I tough that it was a requirement of some specific NAND
technology

BR,

-- 

Andrea SCIAN

DAVE Embedded Systems