Is it an atomic operation for writing a page in NAND flash

[Liu Hui]

Ok, In fact, I am a soft developer, I want to find a way to design a
power-cut safe FTL. I can't control the design of hardware, so I have
to find a common way to ensure atomic operation.

> There is no need for an interrupt, if you have a fast GPIO that you
> can read before each write command that tells if the input power has
> not dropped.
This is no good for performance.

> It's good, but not perfect: In principle a power-failed write could
> successfully store the correct bits including ECC so they read back
> correctly, but with the cell charges not completely stable.  But I
> guess that's rare enough that it is just included in the normal NAND
> bad block possibilities.
Ok, ECC can detect partial write but can't detect unstable cell
charges, I think this is enough since NAND flash is unstable media.

Thanks for your information!
Hui



2010/1/20 Jamie Lokier <jamie at shareable.org>:
> Liu Hui wrote:
>> Richard,
>>
>> Thank you for your confirmation and good idea.
>>
>> I also think about your idea before, that is, when power failure
>> happens, generate an interrupt and blocks any other write requests in
>> interrupt handler. But this is a little complex.
>
> Ideally, you would design the hardware so that power failure can be
> detected early near the power input, but with enough on-board power
> retention (i.e. capacitor) that there is guaranteed enough continuous
> power for the CPU to react and the NAND chip to have enough stable
> power to complete the write reliably.
>
> There is no need for an interrupt, if you have a fast GPIO that you
> can read before each write command that tells if the input power has
> not dropped.
>
>> Now, I think I can use ECC to check the partial write, if a write was
>> not finished, the ECC should be wrong, so we can detect this partial
>> write and discard this write. Do you think this is a good idea?
>
> It's good, but not perfect: In principle a power-failed write could
> successfully store the correct bits including ECC so they read back
> correctly, but with the cell charges not completely stable.  But I
> guess that's rare enough that it is just included in the normal NAND
> bad block possibilities.
>
> -- Jamie
>



-- 
Thanks & Best Regards
Liu Hui
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