Is it an atomic operation for writing a page in NAND flash

[Ricard Wanderlof]

On Wed, 20 Jan 2010, Liu Hui wrote:

>> It's good, but not perfect: In principle a power-failed write could
>> successfully store the correct bits including ECC so they read back
>> correctly, but with the cell charges not completely stable.  But I
>> guess that's rare enough that it is just included in the normal NAND
>> bad block possibilities.
> Ok, ECC can detect partial write but can't detect unstable cell
> charges, I think this is enough since NAND flash is unstable media.

ECC is designed to correct a small number of bits (1 bit for the software 
ECC algorithm used by mtd) and detect failure if a couple of more bits are 
bad (2 bits for the mtd algorithm). Beyond that, the results cannot be 
trusted. That means, that if there are, say, 16 incorrect bits in the 
data, the ECC algorithm will not necessarily indicate that there is a 
failure. It might very well indicate that there is a single bit that needs 
correction, or that all bits are correct. It is not a CRC.

The end result is that you can't say "if the ECC says it's ok, the data 
hasn't been corrupted" (which you could with a CRC). The only thing you 
can say (in the case of the mtd ECC algorithm) is "if there is a one-bit 
error in the data, the ECC will correct it" and "if there is a two-bit 
error in the data, the ECC will detect it".

If you really need that kind of check for data integrity, I suppose you 
could add a CRC algorithm to the ECC calculations already being performed 
by mtd, so that any change in the data would be flagged due to a 
mismatching CRC.

/Ricard
-- 
Ricard Wolf Wanderlöf                           ricardw(at)axis.com
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