Is it an atomic operation for writing a page in NAND flash

[Jamie Lokier]

Liu Hui wrote:
> Richard,
> 
> Thank you for your confirmation and good idea.
> 
> I also think about your idea before, that is, when power failure
> happens, generate an interrupt and blocks any other write requests in
> interrupt handler. But this is a little complex.

Ideally, you would design the hardware so that power failure can be
detected early near the power input, but with enough on-board power
retention (i.e. capacitor) that there is guaranteed enough continuous
power for the CPU to react and the NAND chip to have enough stable
power to complete the write reliably.

There is no need for an interrupt, if you have a fast GPIO that you
can read before each write command that tells if the input power has
not dropped.

> Now, I think I can use ECC to check the partial write, if a write was
> not finished, the ECC should be wrong, so we can detect this partial
> write and discard this write. Do you think this is a good idea?

It's good, but not perfect: In principle a power-failed write could
successfully store the correct bits including ECC so they read back
correctly, but with the cell charges not completely stable.  But I
guess that's rare enough that it is just included in the normal NAND
bad block possibilities.

-- Jamie