[PATCH] fio infrastructure

[Jared Hulbert]

In theory this could address some problems I was contemplating earlier
today.  If Jörn vision of large scale flash storage device without the
added FTL overhead is to realized, we'll need this sort of thing.  For
that matter, take the Atom processor line, aren't the newer ones
planning on raw NAND access built in?  If you want to get the
performance a several NAND chips can enable you'd need something like
this, no?

> I really wish I could have tested this with working hardware, but the
> gods are against that idea.  So here is a patch anyway.

What is needed, bare minimum, to test this?  Is access to multiple
bare NAND chips enough?