[PATCH] fio infrastructure

[Jörn Engel]

On Thu, 3 December 2009 03:22:01 -0800, Jared Hulbert wrote:
> 
> In theory this could address some problems I was contemplating earlier
> today.  If Jörn vision of large scale flash storage device without the
> added FTL overhead is to realized, we'll need this sort of thing.  For
> that matter, take the Atom processor line, aren't the newer ones
> planning on raw NAND access built in?  If you want to get the
> performance a several NAND chips can enable you'd need something like
> this, no?

I cannot comment on processor lines, Atom or otherwise.  But afaics the
only alternative to asynchronous operations would be striping.
Disadvantage of striping is that erase block size (and potentially page
size) increases and bad block in one stripe poison good blocks in all
other stripes.  Not too appealing to me.

Plus, you can get all the benefits from striping with fio as well.

> 
> > I really wish I could have tested this with working hardware, but the
> > gods are against that idea.  So here is a patch anyway.
> 
> What is needed, bare minimum, to test this?  Is access to multiple
> bare NAND chips enough?

Yes.

Jörn

-- 
Premature optimization is the root of all evil.
-- Donald Knuth