bus access for NAND parts

[Cliff Brake]

On Wed, Oct 29, 2008 at 7:54 AM, Cliff Brake <cliff.brake at gmail.com> wrote:
> I've been looking at interfacing a raw NAND device to a PXA270 and
> have the following questions.  It seems that most devices simply use a
> chip select for CE.  What is the mechanism that prevents the NAND
> driver from getting pre-empted and another device access toggling the
> read/write stobes and messing up the NAND cycle while the NAND chip
> select is still low?  I see memory barriers that should prevent out of
> order issues, but I've not located any mechanism yet for preventing a
> separate device access from interfering with the NAND access.

Correction -- above should say:  "It seems that most devices simply use a
_GPIO_ for CE".  The chip select is set low in software, and then
multiple bus cycles are run to execute the address and data phases of
the NAND operation.  So what keeps another process from interrupting
this and running a bus cycle while the GPIO for NAND CE is still low
-- which would toggle the strobes to the NAND cs.

Thanks,
Cliff

-- 
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Cliff Brake
http://bec-systems.com