bus access for NAND parts

[Ricard Wanderlof]

On Thu, 30 Oct 2008, Cliff Brake wrote:

> Correction -- above should say:  "It seems that most devices simply use a
> _GPIO_ for CE".  The chip select is set low in software, and then
> multiple bus cycles are run to execute the address and data phases of
> the NAND operation.  So what keeps another process from interrupting
> this and running a bus cycle while the GPIO for NAND CE is still low
> -- which would toggle the strobes to the NAND cs.

I don't know in general, but in several systems that have multiple buses, 
the NAND flash can be the only device on a particular bus, so conflicts 
with other devices are not an issue in those cases. Otherwise, it would be 
as you say, I agree.

/Ricard
--
Ricard Wolf Wanderlöf                           ricardw(at)axis.com
Axis Communications AB, Lund, Sweden            www.axis.com
Phone +46 46 272 2016                           Fax +46 46 13 61 30