bus access for NAND parts

[Cliff Brake]

I've been looking at interfacing a raw NAND device to a PXA270 and
have the following questions.  It seems that most devices simply use a
chip select for CE.  What is the mechanism that prevents the NAND
driver from getting pre-empted and another device access toggling the
read/write stobes and messing up the NAND cycle while the NAND chip
select is still low?  I see memory barriers that should prevent out of
order issues, but I've not located any mechanism yet for preventing a
separate device access from interfering with the NAND access.

Thanks,
Cliff

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Cliff Brake
http://bec-systems.com