[RFC PATCH 12/22] arm64: dts: ti: k3-j784s4-main: Add DDR nodes for J784S4
MANNURU VENKATESWARLU
v-mannuru at ti.com
Tue Jul 14 05:56:03 PDT 2026
From: Neha Malcom Francis <n-francis at ti.com>
Add DT nodes for the 4 DDR controllers on the J784S4 device. These define
the memory controller with its register regions, interrupts, power
domains, and clock requirements.
This allows for DDR controller temperature monitoring.
Signed-off-by: Neha Malcom Francis <n-francis at ti.com>
Signed-off-by: MANNURU VENKATESWARLU <v-mannuru at ti.com>
---
.../dts/ti/k3-j784s4-j742s2-main-common.dtsi | 83 +++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 73 ++++++++++++++++
2 files changed, 156 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
index c2636e624f18b..65bd68de989f2 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
@@ -2712,4 +2712,87 @@ bist_main14: bist at 33c0000 {
bootph-pre-ram;
ti,sci-dev-id = <234>;
};
+
+ msmc0: msmc {
+ compatible = "ti,j721s2-msmc", "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ intrlv-gran = <0>;
+ intrlv-size = <0>;
+ ecc-enable = <0>;
+ emif-config = <0>;
+ emif-active = <0>;
+ bootph-pre-ram;
+
+ memorycontroller0: memorycontroller at 2980000 {
+ compatible = "ti,j721s2-ddrss";
+ reg = <0x0 0x02990000 0x0 0x4000>,
+ <0x0 0x0114000 0x0 0x100>,
+ <0x0 0x02980000 0x0 0x200>;
+ reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
+ power-domains = <&k3_pds 191 TI_SCI_PD_SHARED>,
+ <&k3_pds 131 TI_SCI_PD_SHARED>;
+ interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x0000 0x00 0x02990000 0x00 0x4000>;
+ ti,ddr-freq0 = <0>;
+ ti,ddr-freq1 = <0>;
+ ti,ddr-freq2 = <0>;
+ ti,ddr-fhs-cnt = <0>;
+ clocks = <&k3_clks 191 1>, <&k3_clks 78 2>;
+ instance = <0>;
+ bootph-pre-ram;
+
+ ddr0: ddr at 0 {
+ compatible = "cdns,k3-ddr";
+ reg = <0x00 0x0000 0x00 0x72c>,
+ <0x00 0x2000 0x00 0x4b0>,
+ <0x00 0x4000 0x00 0x163c>;
+ reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
+ bootph-pre-ram;
+ };
+
+ ddr_pmu0: ddr-pmu at 100 {
+ compatible = "ti,k3-ddr-pmu";
+ reg = <0x00 0x100 0x00 0x14>;
+ };
+ };
+
+ memorycontroller1: memorycontroller at 29a0000 {
+ compatible = "ti,j721s2-ddrss";
+ reg = <0x0 0x029b0000 0x0 0x4000>,
+ <0x0 0x0114000 0x0 0x100>,
+ <0x0 0x029a0000 0x0 0x200>;
+ reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
+ power-domains = <&k3_pds 192 TI_SCI_PD_SHARED>,
+ <&k3_pds 132 TI_SCI_PD_SHARED>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x0000 0x00 0x029b0000 0x00 0x4000>;
+ ti,ddr-freq0 = <0>;
+ ti,ddr-freq1 = <0>;
+ ti,ddr-freq2 = <0>;
+ ti,ddr-fhs-cnt = <0>;
+ clocks = <&k3_clks 192 1>, <&k3_clks 78 2>;
+ instance = <1>;
+ bootph-pre-ram;
+
+ ddr1: ddr at 0 {
+ compatible = "cdns,k3-ddr";
+ reg = <0x00 0x0000 0x00 0x72c>,
+ <0x00 0x2000 0x00 0x4b0>,
+ <0x00 0x4000 0x00 0x163c>;
+ reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
+ bootph-pre-ram;
+ };
+
+ ddr_pmu1: ddr-pmu at 100 {
+ compatible = "ti,k3-ddr-pmu";
+ reg = <0x00 0x100 0x00 0x14>;
+ };
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 78fcd0c40abcf..6c19bda71565f 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -149,6 +149,79 @@ c71_3: dsp at 67800000 {
ti,sci-proc-ids = <0x33 0xff>;
status = "disabled";
};
+
+};
+
+&msmc0 {
+ memorycontroller2: memorycontroller at 29c0000 {
+ compatible = "ti,j721s2-ddrss";
+ reg = <0x0 0x029d0000 0x0 0x4000>,
+ <0x0 0x0114000 0x0 0x100>,
+ <0x0 0x029c0000 0x0 0x200>;
+ reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
+ power-domains = <&k3_pds 193 TI_SCI_PD_SHARED>,
+ <&k3_pds 133 TI_SCI_PD_SHARED>;
+ interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x0000 0x00 0x029d0000 0x00 0x4000>;
+ ti,ddr-freq0 = <0>;
+ ti,ddr-freq1 = <0>;
+ ti,ddr-freq2 = <0>;
+ ti,ddr-fhs-cnt = <0>;
+ clocks = <&k3_clks 193 1>, <&k3_clks 78 2>;
+ instance = <2>;
+ bootph-pre-ram;
+
+ ddr2: ddr at 0 {
+ compatible = "cdns,k3-ddr";
+ reg = <0x00 0x0000 0x00 0x72c>,
+ <0x00 0x2000 0x00 0x4b0>,
+ <0x00 0x4000 0x00 0x163c>;
+ reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
+ bootph-pre-ram;
+ };
+
+ ddr_pmu2: ddr-pmu at 100 {
+ compatible = "ti,k3-ddr-pmu";
+ reg = <0x00 0x100 0x00 0x14>;
+ };
+ };
+
+ memorycontroller3: memorycontroller at 29e0000 {
+ compatible = "ti,j721s2-ddrss";
+ reg = <0x0 0x029f0000 0x0 0x4000>,
+ <0x0 0x0114000 0x0 0x100>,
+ <0x0 0x029e0000 0x0 0x200>;
+ reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
+ power-domains = <&k3_pds 194 TI_SCI_PD_SHARED>,
+ <&k3_pds 139 TI_SCI_PD_SHARED>;
+ interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x0000 0x00 0x029f0000 0x00 0x4000>;
+ ti,ddr-freq0 = <0>;
+ ti,ddr-freq1 = <0>;
+ ti,ddr-freq2 = <0>;
+ ti,ddr-fhs-cnt = <0>;
+ clocks = <&k3_clks 194 1>, <&k3_clks 78 2>;
+ instance = <3>;
+ bootph-pre-ram;
+
+ ddr3: ddr at 0 {
+ compatible = "cdns,k3-ddr";
+ reg = <0x00 0x0000 0x00 0x72c>,
+ <0x00 0x2000 0x00 0x4b0>,
+ <0x00 0x4000 0x00 0x163c>;
+ reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
+ bootph-pre-ram;
+ };
+
+ ddr_pmu3: ddr-pmu at 100 {
+ compatible = "ti,k3-ddr-pmu";
+ reg = <0x00 0x100 0x00 0x14>;
+ };
+ };
};
&scm_conf {
--
2.34.1
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