[RFC PATCH 10/22] arm64: dts: ti: k3-j721e: Add DDR and controller node

[MANNURU VENKATESWARLU]

From: Neha Malcom Francis <n-francis at ti.com>

Add DDR Controller and LPDDR4 node for J721E device. This defines the
memory controller with its register regions, interrupts, power domains
and clock requirements.

Signed-off-by: Neha Malcom Francis <n-francis at ti.com>
Signed-off-by: Gandhar Deshpande <g-deshpande at ti.com>
Signed-off-by: MANNURU VENKATESWARLU <v-mannuru at ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 32 +++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index d5fd30a01032f..67f1bb700f9a9 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -2928,4 +2928,36 @@ main_esm: esm at 700000 {
 		bootph-pre-ram;
 		ti,esm-pins = <344>, <345>;
 	};
+
+	memorycontroller: memorycontroller at 2980000 {
+		compatible = "ti,j721e-ddrss";
+		reg = <0x0 0x02990000 0x0 0x4000>,
+		      <0x0 0x0114000 0x0 0x100>;
+		reg-names = "cfg", "ctrl_mmr_lp4";
+		power-domains = <&k3_pds 47 TI_SCI_PD_SHARED>,
+				<&k3_pds 90 TI_SCI_PD_SHARED>;
+		interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0x00 0x0000 0x00 0x02990000 0x00 0x4000>;
+		ti,ddr-freq1   = <0>;
+		ti,ddr-freq2   = <0>;
+		ti,ddr-fhs-cnt = <0>;
+		clocks = <&k3_clks 47 2>, <&k3_clks 30 9>;
+		bootph-pre-ram;
+
+		ddr: ddr at 0 {
+			compatible = "cdns,k3-ddr";
+			reg = <0x00 0x0000 0x00 0x72c>,
+			      <0x00 0x2000 0x00 0x4b0>,
+			      <0x00 0x4000 0x00 0x163c>;
+			reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
+			bootph-pre-ram;
+		};
+
+		ddr_pmu0: ddr-pmu at 100 {
+			compatible = "ti,k3-ddr-pmu";
+			reg = <0x00 0x100 0x00 0x14>;
+		};
+	};
 };
-- 
2.34.1