[RFC PATCH 13/22] arm64: dts: ti: k3-am62: Add DDR and controller node

[MANNURU VENKATESWARLU]

From: Santhosh Kumar K <s-k6 at ti.com>

Add DDR Controller and LPDDR4 node for AM62x device. This defines the
memory controller with its register regions, interrupts, power domains
and clock requirements.

Signed-off-by: Santhosh Kumar K <s-k6 at ti.com>
Signed-off-by: Gandhar Deshpande <g-deshpande at ti.com>
Signed-off-by: Neha Malcom Francis <n-francis at ti.com>
Signed-off-by: MANNURU VENKATESWARLU <v-mannuru at ti.com>
---
 arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 25 ++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
index c5ee263d34a62..d873928c1bdd9 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
@@ -1265,4 +1265,29 @@ elm0: ecc at 25010000 {
 		clock-names = "fck";
 		status = "disabled";
 	};
+
+	memory-controller at f300000 {
+		compatible = "ti,am62-ddrss";
+		reg = <0x00 0x0f300000 0x00 0x200>;
+		reg-names = "ss_cfg";
+		ranges = <0x00 0x00 0x00 0x0f308000 0x00 0x55f8>;
+		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 170 0>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		ddr: ddr at 0 {
+			compatible = "cdns,k3-ddr";
+			reg = <0x00 0x0000 0x00 0x69c>,
+				<0x00 0x2000 0x00 0x564>,
+				<0x00 0x4000 0x00 0x15f8>;
+			reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
+		};
+
+		ddr_pmu0: ddr-pmu at 100 {
+			compatible = "ti,k3-ddr-pmu";
+			reg = <0x00 0x100 0x00 0x14>;
+		};
+	};
 };
-- 
2.34.1