[boot-wrapper PATCH 3/4] aarch64: enable access to HACDBS and HDBSS system registers

[Andre Przywara]

ARMv9.5 introduced FEAT_HAFDBS and FEAT_HACBDS, both of which introduce
system registers accessible from EL1 and EL2. Access to them is guarded
by SCR_EL3 control bits HDBSSEn and HACDBSEn.

Since boot-wrapper has no business in limiting those features or trapping
access to those register, set the no-trap bits in SCR_EL3, if we detect
the respective CPU feature bits.

Signed-off-by: Andre Przywara <andre.przywara at arm.com>
---
 arch/aarch64/include/asm/cpu.h | 6 ++++++
 arch/aarch64/init.c            | 6 ++++++
 2 files changed, 12 insertions(+)

diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
index 1d86c23..9c794be 100644
--- a/arch/aarch64/include/asm/cpu.h
+++ b/arch/aarch64/include/asm/cpu.h
@@ -83,6 +83,8 @@
 #define SCR_EL3_EnFPM			BIT(50)
 #define SCR_EL3_PFAREn			BIT(53)
 #define SCR_EL3_FGTEN2			BIT(59)
+#define SCR_EL3_HDBSSEn			BIT(60)
+#define SCR_EL3_HACDBSEn		BIT(61)
 
 #define VTCR_EL2_MSA			BIT(31)
 
@@ -113,6 +115,7 @@
 #define ID_AA64MMFR0_EL1_FGT		BITS(59, 56)
 #define ID_AA64MMFR0_EL1_ECV		BITS(63, 60)
 
+#define ID_AA64MMFR1_EL1_HAFDBS		BITS(3, 0)
 #define ID_AA64MMFR1_EL1_HCX		BITS(43, 40)
 
 #define ID_AA64MMFR3_EL1_TCRX		BITS(3, 0)
@@ -124,6 +127,9 @@
 #define ID_AA64MMFR3_EL1_AIE		BITS(27, 24)
 #define ID_AA64MMFR3_EL1_D128		BITS(35, 32)
 
+#define ID_AA64MMFR4_EL1		s3_0_c0_c7_4
+#define ID_AA64MMFR4_EL1_HACDBS		BITS(15, 12)
+
 #define ID_AA64PFR0_EL1_RAS		BITS(31, 28)
 #define ID_AA64PFR0_EL1_SVE		BITS(35, 32)
 #define ID_AA64PFR0_EL1_MPAM		BITS(43, 40)
diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
index 004149f..05637d4 100644
--- a/arch/aarch64/init.c
+++ b/arch/aarch64/init.c
@@ -142,6 +142,12 @@ static void cpu_init_el3(void)
 	if (mrs_field(ID_AA64PFR1_EL1, PFAR))
 		scr |= SCR_EL3_PFAREn;
 
+	if (mrs_field(ID_AA64MMFR4_EL1, HACDBS))
+		scr |= SCR_EL3_HACDBSEn;
+
+	if (mrs_field(ID_AA64MMFR1_EL1, HAFDBS) >= 4)
+		scr |= SCR_EL3_HDBSSEn;
+
 	msr(SCR_EL3, scr);
 
 	msr(CPTR_EL3, cptr);
-- 
2.25.1