[boot-wrapper PATCH 4/4] aarch64: enable access to FEAT_RASv1p1 system registers

[Andre Przywara]

FEAT_RASv1p1 introduces RAS error injection system registers, access to
which is protected by an SCR_EL3 bit.

Since boot-wrapper has no business in limiting those features or trapping
access to those register, set the no-trap bit in SCR_EL3, if we detect
the respective CPU feature bit.

Signed-off-by: Andre Przywara <andre.przywara at arm.com>
---
 arch/aarch64/include/asm/cpu.h | 1 +
 arch/aarch64/init.c            | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
index 9c794be..f4b7818 100644
--- a/arch/aarch64/include/asm/cpu.h
+++ b/arch/aarch64/include/asm/cpu.h
@@ -68,6 +68,7 @@
 #define SCR_EL3_RW			BIT(10)
 #define SCR_EL3_APK			BIT(16)
 #define SCR_EL3_API			BIT(17)
+#define SCR_EL3_FIEN			BIT(21)
 #define SCR_EL3_ATA			BIT(26)
 #define SCR_EL3_FGTEN			BIT(27)
 #define SCR_EL3_ECVEN			BIT(28)
diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
index 05637d4..704471f 100644
--- a/arch/aarch64/init.c
+++ b/arch/aarch64/init.c
@@ -133,6 +133,9 @@ static void cpu_init_el3(void)
 	if (mrs_field(ID_AA64PFR1_EL1, THE))
 		scr |= SCR_EL3_RCWMASKEn;
 
+	if (mrs_field(ID_AA64PFR0_EL1, RAS) >= 0b0010)
+		scr |= SCR_EL3_FIEN;
+
 	if (mrs_field(ID_AA64PFR2_EL1, FPMR))
 		scr |= SCR_EL3_EnFPM;
 
-- 
2.25.1