[boot-wrapper PATCH 2/4] aarch64: enable access to FEAT_AIE and FEAT_PFAR features

[Andre Przywara]

ARMv8.9 introduced FEAT_AIE and FEAT_PFAR, both of which introduce
system registers accessible from EL1 and EL2. Access to them is guarded
by SCR_EL3 control bits AIEn and PFAREn.

Since boot-wrapper has no business in limiting those features or trapping
access to those register, set the no-trap bits in SCR_EL3, if we detect
the respective CPU feature bits.

Signed-off-by: Andre Przywara <andre.przywara at arm.com>
---
 arch/aarch64/include/asm/cpu.h | 4 ++++
 arch/aarch64/init.c            | 6 ++++++
 2 files changed, 10 insertions(+)

diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
index 0f6e2ce..1d86c23 100644
--- a/arch/aarch64/include/asm/cpu.h
+++ b/arch/aarch64/include/asm/cpu.h
@@ -78,8 +78,10 @@
 #define SCR_EL3_TCR2EN			BIT(43)
 #define SCR_EL3_SCTLR2En		BIT(44)
 #define SCR_EL3_PIEN			BIT(45)
+#define SCR_EL3_AIEn			BIT(46)
 #define SCR_EL3_D128En			BIT(47)
 #define SCR_EL3_EnFPM			BIT(50)
+#define SCR_EL3_PFAREn			BIT(53)
 #define SCR_EL3_FGTEN2			BIT(59)
 
 #define VTCR_EL2_MSA			BIT(31)
@@ -119,6 +121,7 @@
 #define ID_AA64MMFR3_EL1_S2PIE		BITS(15, 12)
 #define ID_AA64MMFR3_EL1_S1POE		BITS(19, 16)
 #define ID_AA64MMFR3_EL1_S2POE		BITS(23, 20)
+#define ID_AA64MMFR3_EL1_AIE		BITS(27, 24)
 #define ID_AA64MMFR3_EL1_D128		BITS(35, 32)
 
 #define ID_AA64PFR0_EL1_RAS		BITS(31, 28)
@@ -130,6 +133,7 @@
 #define ID_AA64PFR1_EL1_SME		BITS(27, 24)
 #define ID_AA64PFR1_EL1_CSV2_frac	BITS(35, 32)
 #define ID_AA64PFR1_EL1_THE		BITS(51, 48)
+#define ID_AA64PFR1_EL1_PFAR		BITS(63, 60)
 
 #define ID_AA64PFR2_EL1			s3_0_c0_c4_2
 #define ID_AA64PFR2_EL1_FPMR		BITS(35, 32)
diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
index 99e43cf..004149f 100644
--- a/arch/aarch64/init.c
+++ b/arch/aarch64/init.c
@@ -136,6 +136,12 @@ static void cpu_init_el3(void)
 	if (mrs_field(ID_AA64PFR2_EL1, FPMR))
 		scr |= SCR_EL3_EnFPM;
 
+	if (mrs_field(ID_AA64MMFR3_EL1, AIE))
+		scr |= SCR_EL3_AIEn;
+
+	if (mrs_field(ID_AA64PFR1_EL1, PFAR))
+		scr |= SCR_EL3_PFAREn;
+
 	msr(SCR_EL3, scr);
 
 	msr(CPTR_EL3, cptr);
-- 
2.25.1