Reset controller on the Amlogic SoC board.

[Neil Armstrong]

Hi Anand,

On 23/07/2020 12:49, Anand Moon wrote:
> Hi Neil / Martin / Jerome / Kevin.
> 
> I am a bit investigating the reset controller for the Amlogic SoC board.
> Each of thes reset controllers have different reset IP features.
> So we should map the reset controller to appropriate IP nodes
> in the DTS to make this work.

Correct support is already done for Meson8/8b/GXL/GXBB/G12A/A1.

Can you specify which features are missing ?

> 
> Following are the reset controller reg ip blocks as per the Datasheet
> Datasheet :- S805_Datasheet V0.8 20150126
> Datasheet :- S905X_Datasheet V0.3 20170314publicversion-Wesion
> On GXBB / GLX
> RESET_REGISTER   ----> 0xc11004404
> RESET1_REGISTER ----> 0xc11004408
> RESET2_REGISTER ----> 0xc1100440c
> RESET3_REGISTER ----> 0xc11004410
> RESET4_REGISTER ----> 0xc11004414
> RESET5_REGISTER ----> 0xc1100441c
> RESET6_REGISTER ----> 0xc11004420
> 
> DataSheet - S922X_Public_Datasheet_V0.2-Hardkernel.pdf
> G12B / S905X3
> RESET0_REGISTER ---> 0xFFD01004
> RESET1_REGISTER ---> 0xFFD01008
> RESET2_REGISTER ---> 0xFFD0100C
> RESET3_REGISTER ---> 0xFFD01010
> RESET4_REGISTER ---> 0xFFD01014
> RESET5_REGISTER ---> 0xFFD0101c
> RESET7_REGISTER ---> 0xFFD01020
> 
> Each of the reset controllers have some different bit fields,
> For that we need to have reset binding macros accordingly.

It's a documentation issue, the register layout is the same from Meson8
to G12A.

Neil

> 
> Please share your thoughts and If you have some inputs or
> another approach please let me know.
> I just want your feedback before preparing
> and submitting some patches.
> 
> Sorry my English is a bit poor to express hope you
> will understand what changes I am proposing.
> 
> -Anand
>