[PATCH 3/7] PCI: imx6: Fix waiting for link up

[Marek Vasut]

While waiting for the PHY to report the PCIe link is up, we might
hit a situation where the link training is still in progress, while
the PHY already reports the link is up. Add additional check for
this condition.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Bjorn Helgaas <bhelgaas at google.com>
Cc: Frank Li <lznuaa at gmail.com>
Cc: Harro Haan <hrhaan at gmail.com>
Cc: Jingoo Han <jg1.han at samsung.com>
Cc: Mohit KUMAR <Mohit.KUMAR at st.com>
Cc: Pratyush Anand <pratyush.anand at st.com>
Cc: Richard Zhu <r65037 at freescale.com>
Cc: Sascha Hauer <s.hauer at pengutronix.de>
Cc: Sean Cross <xobs at kosagi.com>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Siva Reddy Kallam <siva.kallam at samsung.com>
Cc: Srikanth T Shivanand <ts.srikanth at samsung.com>
Cc: Tim Harvey <tharvey at gateworks.com>
Cc: Troy Kisky <troy.kisky at boundarydevices.com>
Cc: Yinghai Lu <yinghai at kernel.org>
---
 drivers/pci/host/pci-imx6.c | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
index 52027ad..4d5be4e 100644
--- a/drivers/pci/host/pci-imx6.c
+++ b/drivers/pci/host/pci-imx6.c
@@ -48,6 +48,8 @@ struct imx6_pcie {
 #define PL_OFFSET 0x700
 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
+#define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING	(1 << 29)
+#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP		(1 << 4)
 
 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
 #define PCIE_PHY_CTRL_DATA_LOC 0
@@ -338,10 +340,17 @@ static int imx6_pcie_link_up(struct pcie_port *pp)
 {
 	u32 rc, ltssm, rx_valid, temp;
 
-	/* link is debug bit 36, debug register 1 starts at bit 32 */
-	rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) & (0x1 << (36 - 32));
-	if (rc)
-		return -EAGAIN;
+	/*
+	 * Test if the PHY reports that the link is up and also that
+	 * the link training finished. It might happen that the PHY
+	 * reports the link is already up, but the link training bit
+	 * is still set, so make sure to check the training is done
+	 * as well here.
+	 */
+	rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
+	if ((rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP) &&
+	    !(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING))
+		return 1;
 
 	/*
 	 * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
-- 
1.8.4.3