L1 & L2 cache flush sequence on CortexA5 MPcore w.r.t low power modes

[Lorenzo Pieralisi]

On Wed, Sep 19, 2012 at 09:55:52AM +0100, Antti P Miettinen wrote:
> Lorenzo Pieralisi <lorenzo.pieralisi at arm.com> writes:
> > What we should do as I described, is executing the sequence:
> >
> > clear SCTRL.C
> > clean cache
> > exit coherency
> 
> How does SCTRL.C affect TLB fetches? Especially on A9? Seems that page
> table updates do clean_dcache_area() so probably not an issue but just
> out of curiosity, are TLB fetches affected by the C bit on A9?

Yes, they are. TLB fetches cannot search the D-cache if the C bit in
SCTLR is clear on A9. I do not see any issue with this though, at least
in the power down procedure described above and in previous e-mails in
this thread.

Lorenzo