L1 & L2 cache flush sequence on CortexA5 MPcore w.r.t low power modes

[Antti P Miettinen]

Lorenzo Pieralisi <lorenzo.pieralisi at arm.com> writes:
> What we should do as I described, is executing the sequence:
>
> clear SCTRL.C
> clean cache
> exit coherency

How does SCTRL.C affect TLB fetches? Especially on A9? Seems that page
table updates do clean_dcache_area() so probably not an issue but just
out of curiosity, are TLB fetches affected by the C bit on A9?

--
Antti P Miettinen
http://www.iki.fi/~ananaza/