[RFC PATCH 1/5] ARM: OMAP: TI81XX: prcm: Add module and register offsets
Paul Walmsley
paul at pwsan.com
Tue Oct 4 05:31:17 EDT 2011
From: Hemant Pedanekar <hemantp at ti.com>
This patch adds some of the PRCM register offsets for the TI814X and
TI816X devices as required for the clockdomain, powerdomain, clock, and
hwmod data.
This patch is a collaboration between Hemant Pedanekar <hemantp at ti.com>
and Paul Walmsley <paul at pwsan.com>.
---
arch/arm/mach-omap2/Makefile | 1
arch/arm/mach-omap2/prcm814x.h | 62 +++++++++++++
arch/arm/mach-omap2/prcm816x.h | 186 +++++++++++++++++++++++++++++++++++++++
arch/arm/mach-omap2/prcm81xx.c | 32 +++++++
arch/arm/mach-omap2/prcm81xx.h | 193 ++++++++++++++++++++++++++++++++++++++++
5 files changed, 474 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/prcm814x.h
create mode 100644 arch/arm/mach-omap2/prcm816x.h
create mode 100644 arch/arm/mach-omap2/prcm81xx.c
create mode 100644 arch/arm/mach-omap2/prcm81xx.h
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index d4918ca..9c6b185 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -87,6 +87,7 @@ obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm2xxx_3xxx.o cminst44xx.o \
cm44xx.o prcm_mpu44xx.o \
prminst44xx.o vc44xx_data.o \
vp44xx_data.o
+obj-$(CONFIG_SOC_OMAPTI81XX) += prcm81xx.o
# OMAP voltage domains
ifeq ($(CONFIG_PM),y)
diff --git a/arch/arm/mach-omap2/prcm814x.h b/arch/arm/mach-omap2/prcm814x.h
new file mode 100644
index 0000000..82ea300
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm814x.h
@@ -0,0 +1,62 @@
+/*
+ * TI814X-specific PRCM register access macros
+ *
+ * Copyright (C) 2010-2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM814X_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM814X_H
+
+#include "prcm81xx.h"
+
+/* TI814X-specific PRCM instances */
+#define TI814X_CM_HDVICP_INST 0x0600 /* 256B */
+#define TI814X_CM_ISP_INST 0x0700 /* 256B */
+#define TI814X_CM_DSS_INST 0x0800 /* 256B */
+#define TI814X_PRM_HDVICP_INST 0x0c00 /* 256B */
+#define TI814X_PRM_ISP_INST 0x0d00 /* 256B */
+#define TI814X_PRM_DSS_INST 0x0e00 /* 256B */
+#define TI814X_PRM_ALWON_INST 0x1800 /* 1KiB */
+
+
+/*
+ * TI814x-specific PRCM registers offsets. The offsets below are
+ * relative to the PRCM instance base.
+ */
+
+/* CM_ALWON */
+#define TI814X_CM_ALWON_L3_SLOW_CLKSTCTRL_OFFSET 0x0000
+#define TI814X_CM_ALWON_L3_SLOW_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0000)
+#define TI814X_CM_ALWON_L3_MED_CLKSTCTRL_OFFSET 0x0008
+#define TI814X_CM_ALWON_L3_MED_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0008)
+
+/* CM_HDVICP */
+#define TI814X_CM_HDVICP_CLKSTCTRL_OFFSET 0x0000
+#define TI814X_CM_HDVICP_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_HDVICP_INST, 0x0000)
+
+/* CM_ISP */
+#define TI814X_CM_ISP_CLKSTCTRL_OFFSET 0x0000
+#define TI814X_CM_ISP_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ISP_INST, 0x0000)
+
+/* CM_DSS */
+#define TI814X_CM_DSS_CLKSTCTRL_OFFSET 0x0000
+#define TI814X_CM_DSS_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ISP_INST, 0x0000)
+
+/* CM_DEFAULT */
+#define TI814X_CM_DEFAULT_TPPSS_CLKSTCTRL_OFFSET 0x0000
+#define TI814X_CM_DEFAULT_TPPSS_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0000)
+#define TI814X_CM_DEFAULT_PCI_CLKSTCTRL_OFFSET 0x0004
+#define TI814X_CM_DEFAULT_PCI_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0004)
+#define TI814X_CM_DEFAULT_DUCATI_CLKSTCTRL_OFFSET 0x000c
+#define TI814X_CM_DEFAULT_DUCATI_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x000c)
+
+#endif
diff --git a/arch/arm/mach-omap2/prcm816x.h b/arch/arm/mach-omap2/prcm816x.h
new file mode 100644
index 0000000..74491d9
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm816x.h
@@ -0,0 +1,186 @@
+/*
+ * TI816X-specific PRCM register access macros
+ *
+ * Copyright (C) 2010-2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM816X_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM816X_H
+
+#include "prcm81xx.h"
+
+/*
+ * TI816x-specific PRCM registers offsets. The offsets below are
+ * relative to the PRCM instance base.
+ */
+
+/* CM_DPLL */
+#define TI816X_CM_DPLL_SYSCLK1_CLKSEL_OFFSET 0x0000
+#define TI816X_CM_DPLL_SYSCLK1_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0000)
+#define TI816X_CM_DPLL_SYSCLK2_CLKSEL_OFFSET 0x0004
+#define TI816X_CM_DPLL_SYSCLK2_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0004)
+#define TI816X_CM_DPLL_SYSCLK3_CLKSEL_OFFSET 0x0008
+#define TI816X_CM_DPLL_SYSCLK3_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0008)
+#define TI816X_CM_DPLL_SYSCLK4_CLKSEL_OFFSET 0x000C
+#define TI816X_CM_DPLL_SYSCLK4_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x000C)
+#define TI816X_CM_DPLL_SYSCLK5_CLKSEL_OFFSET 0x0010
+#define TI816X_CM_DPLL_SYSCLK5_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0010)
+#define TI816X_CM_DPLL_SYSCLK6_CLKSEL_OFFSET 0x0014
+#define TI816X_CM_DPLL_SYSCLK6_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0014)
+#define TI816X_CM_DPLL_SYSCLK7_CLKSEL_OFFSET 0x0018
+#define TI816X_CM_DPLL_SYSCLK7_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0018)
+#define TI816X_CM_DPLL_SYSCLK10_CLKSEL_OFFSET 0x0024
+#define TI816X_CM_DPLL_SYSCLK10_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0024)
+#define TI816X_CM_DPLL_SYSCLK11_CLKSEL_OFFSET 0x002C
+#define TI816X_CM_DPLL_SYSCLK11_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x002C)
+#define TI816X_CM_DPLL_SYSCLK12_CLKSEL_OFFSET 0x0030
+#define TI816X_CM_DPLL_SYSCLK12_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0030)
+#define TI816X_CM_DPLL_SYSCLK13_CLKSEL_OFFSET 0x0034
+#define TI816X_CM_DPLL_SYSCLK13_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0034)
+#define TI816X_CM_DPLL_SYSCLK15_CLKSEL_OFFSET 0x0038
+#define TI816X_CM_DPLL_SYSCLK15_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0038)
+#define TI816X_CM_DPLL_VPB3_CLKSEL_OFFSET 0x0040
+#define TI816X_CM_DPLL_VPB3_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0040)
+#define TI816X_CM_DPLL_VPC1_CLKSEL_OFFSET 0x0044
+#define TI816X_CM_DPLL_VPC1_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0044)
+#define TI816X_CM_DPLL_VPD1_CLKSEL_OFFSET 0x0048
+#define TI816X_CM_DPLL_VPD1_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0048)
+#define TI816X_CM_DPLL_SYSCLK19_CLKSEL_OFFSET 0x004C
+#define TI816X_CM_DPLL_SYSCLK19_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x004C)
+#define TI816X_CM_DPLL_SYSCLK20_CLKSEL_OFFSET 0x0050
+#define TI816X_CM_DPLL_SYSCLK20_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0050)
+#define TI816X_CM_DPLL_SYSCLK21_CLKSEL_OFFSET 0x0054
+#define TI816X_CM_DPLL_SYSCLK21_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0054)
+#define TI816X_CM_DPLL_SYSCLK22_CLKSEL_OFFSET 0x0058
+#define TI816X_CM_DPLL_SYSCLK22_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0058)
+#define TI816X_CM_DPLL_APA_CLKSEL_OFFSET 0x005C
+#define TI816X_CM_DPLL_APA_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x005C)
+#define TI816X_CM_DPLL_SYSCLK14_CLKSEL_OFFSET 0x0070
+#define TI816X_CM_DPLL_SYSCLK14_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0070)
+#define TI816X_CM_DPLL_SYSCLK16_CLKSEL_OFFSET 0x0074
+#define TI816X_CM_DPLL_SYSCLK16_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0074)
+#define TI816X_CM_DPLL_SYSCLK18_CLKSEL_OFFSET 0x0078
+#define TI816X_CM_DPLL_SYSCLK18_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0078)
+#define TI816X_CM_DPLL_AUDIOCLK_MCASP0_CLKSEL_OFFSET 0x007C
+#define TI816X_CM_DPLL_AUDIOCLK_MCASP0_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x007C)
+#define TI816X_CM_DPLL_AUDIOCLK_MCASP1_CLKSEL_OFFSET 0x0080
+#define TI816X_CM_DPLL_AUDIOCLK_MCASP1_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0080)
+#define TI816X_CM_DPLL_AUDIOCLK_MCASP2_CLKSEL_OFFSET 0x0084
+#define TI816X_CM_DPLL_AUDIOCLK_MCASP2_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0084)
+#define TI816X_CM_DPLL_AUDIOCLK_MCBSP_CLKSEL_OFFSET 0x0088
+#define TI816X_CM_DPLL_AUDIOCLK_MCBSP_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0088)
+#define TI816X_CM_DPLL_TIMER1_CLKSEL_OFFSET 0x0090
+#define TI816X_CM_DPLL_TIMER1_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0090)
+#define TI816X_CM_DPLL_TIMER2_CLKSEL_OFFSET 0x0094
+#define TI816X_CM_DPLL_TIMER2_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0094)
+#define TI816X_CM_DPLL_TIMER3_CLKSEL_OFFSET 0x0098
+#define TI816X_CM_DPLL_TIMER3_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0098)
+#define TI816X_CM_DPLL_TIMER4_CLKSEL_OFFSET 0x009C
+#define TI816X_CM_DPLL_TIMER4_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x009C)
+#define TI816X_CM_DPLL_TIMER5_CLKSEL_OFFSET 0x00A0
+#define TI816X_CM_DPLL_TIMER5_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x00A0)
+#define TI816X_CM_DPLL_TIMER6_CLKSEL_OFFSET 0x00A4
+#define TI816X_CM_DPLL_TIMER6_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x00A4)
+#define TI816X_CM_DPLL_TIMER7_CLKSEL_OFFSET 0x00A8
+#define TI816X_CM_DPLL_TIMER7_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x00A8)
+#define TI816X_CM_DPLL_HDMI_CLKSEL_OFFSET 0x00AC
+#define TI816X_CM_DPLL_HDMI_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x00AC)
+#define TI816X_CM_DPLL_SYSCLK23_CLKSEL_OFFSET 0x00B0
+#define TI816X_CM_DPLL_SYSCLK23_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x00B0)
+#define TI816X_CM_DPLL_SYSCLK24_CLKSEL_OFFSET 0x00B4
+#define TI816X_CM_DPLL_SYSCLK24_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x00B4)
+
+/* CM_DEFAULT */
+#define TI816X_CM_DEFAULT_L3_MED_CLKSTCTRL_OFFSET 0x0004
+#define TI816X_CM_DEFAULT_L3_MED_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0004)
+#define TI816X_CM_DEFAULT_L3_FAST_CLKSTCTRL_OFFSET 0x0008
+#define TI816X_CM_DEFAULT_L3_FAST_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0008)
+#define TI816X_CM_DEFAULT_TPPSS_CLKSTCTRL_OFFSET 0x000C
+#define TI816X_CM_DEFAULT_TPPSS_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x000C)
+#define TI816X_CM_DEFAULT_PCI_CLKSTCTRL_OFFSET 0x0010
+#define TI816X_CM_DEFAULT_PCI_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0010)
+#define TI816X_CM_DEFAULT_L3_SLOW_CLKSTCTRL_OFFSET 0x0014
+#define TI816X_CM_DEFAULT_L3_SLOW_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0014)
+#define TI816X_CM_DEFAULT_DUCATI_CLKSTCTRL_OFFSET 0x0018
+#define TI816X_CM_DEFAULT_DUCATI_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0018)
+#define TI816X_CM_DEFAULT_EMIF_0_CLKCTRL_OFFSET 0x0020
+#define TI816X_CM_DEFAULT_EMIF_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0020)
+#define TI816X_CM_DEFAULT_EMIF_1_CLKCTRL_OFFSET 0x0024
+#define TI816X_CM_DEFAULT_EMIF_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0024)
+#define TI816X_CM_DEFAULT_DMM_CLKCTRL_OFFSET 0x0028
+#define TI816X_CM_DEFAULT_DMM_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0028)
+#define TI816X_CM_DEFAULT_FW_CLKCTRL_OFFSET 0x002C
+#define TI816X_CM_DEFAULT_FW_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x002C)
+#define TI816X_CM_DEFAULT_TPPSS_CLKCTRL_OFFSET 0x0054
+#define TI816X_CM_DEFAULT_TPPSS_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0054)
+#define TI816X_CM_DEFAULT_USB_CLKCTRL_OFFSET 0x0058
+#define TI816X_CM_DEFAULT_USB_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0058)
+#define TI816X_CM_DEFAULT_SATA_CLKCTRL_OFFSET 0x0060
+#define TI816X_CM_DEFAULT_SATA_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0060)
+#define TI816X_CM_DEFAULT_DUCATI_CLKCTRL_OFFSET 0x0074
+#define TI816X_CM_DEFAULT_DUCATI_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0074)
+#define TI816X_CM_DEFAULT_PCI_CLKCTRL_OFFSET 0x0078
+#define TI816X_CM_DEFAULT_PCI_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0078)
+
+/* CM_ALWON */
+#define TI816X_CM_ALWON_OCMC_1_CLKSTCTRL_OFFSET 0x0018
+#define TI816X_CM_ALWON_OCMC_1_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0018)
+#define TI816X_CM_ALWON_MPU_CLKSTCTRL_OFFSET 0x001C
+#define TI816X_CM_ALWON_MPU_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x001C)
+#define TI816X_CM_ALWON_TIMER_0_CLKCTRL_OFFSET 0x016C
+#define TI816X_CM_ALWON_TIMER_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x016C)
+#define TI816X_CM_ALWON_TIMER_1_CLKCTRL_OFFSET 0x0170
+#define TI816X_CM_ALWON_TIMER_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0170)
+#define TI816X_CM_ALWON_TIMER_2_CLKCTRL_OFFSET 0x0174
+#define TI816X_CM_ALWON_TIMER_2_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0174)
+#define TI816X_CM_ALWON_TIMER_3_CLKCTRL_OFFSET 0x0178
+#define TI816X_CM_ALWON_TIMER_3_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0178)
+#define TI816X_CM_ALWON_TIMER_5_CLKCTRL_OFFSET 0x0180
+#define TI816X_CM_ALWON_TIMER_5_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0180)
+#define TI816X_CM_ALWON_TIMER_6_CLKCTRL_OFFSET 0x0184
+#define TI816X_CM_ALWON_TIMER_6_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0184)
+#define TI816X_CM_ALWON_TIMER_7_CLKCTRL_OFFSET 0x0188
+#define TI816X_CM_ALWON_TIMER_7_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0188)
+#define TI816X_CM_ALWON_OCMC_1_CLKCTRL_OFFSET 0x01B8
+#define TI816X_CM_ALWON_OCMC_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01B8)
+#define TI816X_CM_ALWON_SMARTCARD_0_CLKCTR_OFFSET 0x01BC
+#define TI816X_CM_ALWON_SMARTCARD_0_CLKCTR TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01BC)
+#define TI816X_CM_ALWON_SMARTCARD_1_CLKCTR_OFFSET 0x01C0
+#define TI816X_CM_ALWON_SMARTCARD_1_CLKCTR TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01C0)
+#define TI816X_CM_ALWON_SECSS_CLKCTRL_OFFSET 0x01C8
+#define TI816X_CM_ALWON_SECSS_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01C8)
+#define TI816X_CM_ALWON_SR_2_CLKCTRL_OFFSET 0x0210
+#define TI816X_CM_ALWON_SR_2_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0210)
+#define TI816X_CM_ALWON_SR_3_CLKCTRL_OFFSET 0x0214
+#define TI816X_CM_ALWON_SR_3_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0214)
+#define TI816X_CM_ALWON_SR_4_CLKCTRL_OFFSET 0x0218
+#define TI816X_CM_ALWON_SR_4_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0218)
+#define TI816X_CM_ALWON_SR_5_CLKCTRL_OFFSET 0x021C
+#define TI816X_CM_ALWON_SR_5_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x021C)
+#define TI816X_CM_ALWON_SR_6_CLKCTRL_OFFSET 0x0220
+#define TI816X_CM_ALWON_SR_6_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0220)
+#define TI816X_CM_ALWON_SR_7_CLKCTRL_OFFSET 0x0224
+#define TI816X_CM_ALWON_SR_7_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0224)
+#define TI816X_CM_ALWON_CUST_EFUSE_CLKCTRL_OFFSET 0x0228
+#define TI816X_CM_ALWON_CUST_EFUSE_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0228)
+
+/* CM_ACTIVE */
+#define TI816X_CM_ACTIVE_HDDSS_CLKSTCTRL_OFFSET 0x0004
+#define TI816X_CM_ACTIVE_HDDSS_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ACTIVE_INST, 0x0004)
+#define TI816X_CM_ACTIVE_HDMI_CLKSTCTRL_OFFSET 0x0008
+#define TI816X_CM_ACTIVE_HDMI_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ACTIVE_INST, 0x0008)
+#define TI816X_CM_ACTIVE_HDDSS_CLKCTRL_OFFSET 0x0024
+#define TI816X_CM_ACTIVE_HDDSS_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ACTIVE_INST, 0x0024)
+#define TI816X_CM_ACTIVE_HDMI_CLKCTRL_OFFSET 0x0028
+#define TI816X_CM_ACTIVE_HDMI_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ACTIVE_INST, 0x0028)
+
+#endif
diff --git a/arch/arm/mach-omap2/prcm81xx.c b/arch/arm/mach-omap2/prcm81xx.c
new file mode 100644
index 0000000..d48e5fc
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm81xx.c
@@ -0,0 +1,32 @@
+/*
+ * TI81XX PRCM register access functions
+ *
+ * Copyright (C) 2010-2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+
+#include "prcm81xx.h"
+
+static u32 ti81xx_prcm_inst_read(u16 inst, u16 offs)
+{
+ return __raw_readl(prm_base + inst + offs);
+}
+
+static void ti81xx_prcm_inst_write(u32 v, u16 inst, u16 offs)
+{
+ __raw_writel(v, prm_base + inst + offs);
+}
+
+
diff --git a/arch/arm/mach-omap2/prcm81xx.h b/arch/arm/mach-omap2/prcm81xx.h
new file mode 100644
index 0000000..fd0a174
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm81xx.h
@@ -0,0 +1,193 @@
+/*
+ * TI81XX PRCM register access macros and module offsets
+ *
+ * Copyright (C) 2010-2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM81XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM81XX_H
+
+#include "prcm-common.h"
+
+#define TI81XX_PRCM_REGADDR(instance, reg) \
+ OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE + (instance) + (reg))
+
+/*
+ * TI81XX-common PRM/CM instance offsets
+ */
+#define TI81XX_PRM_DEVICE_INST 0x0000 /* 256B */
+#define TI81XX_CM_DEVICE_INST 0x0100 /* 256B */
+#define TI81XX_PRM_OCP_SOCKET_INST 0x0200 /* 256B */
+#define TI81XX_CM_DPLL_INST 0x0300 /* 256B */
+#define TI81XX_CM_ACTIVE_INST 0x0400 /* 256B */
+#define TI81XX_CM_DEFAULT_INST 0x0500 /* 256B */
+#define TI81XX_CM_SGX_INST 0x0900 /* 256B */
+#define TI81XX_PRM_ACTIVE_INST 0x0a00 /* 256B */
+#define TI81XX_PRM_DEFAULT_INST 0x0b00 /* 256B */
+#define TI81XX_PRM_SGX_INST 0x0f00 /* 256B */
+#define TI81XX_CM_ALWON_INST 0x1400 /* 1KB */
+
+/*
+ * TI81xx-common register offsets
+ */
+
+/* PRM_DEVICE */
+#define TI81XX_PRM_DEVICE_RSTCTRL_OFFSET 0x0000
+#define TI81XX_PRM_DEVICE_RSTCTRL TI81XX_PRCM_REGADDR(TI81XX_PRM_DEVICE_INST, 0x0000)
+#define TI81XX_PRM_DEVICE_RSTTIME_OFFSET 0x0004
+#define TI81XX_PRM_DEVICE_RSTTIME TI81XX_PRCM_REGADDR(TI81XX_PRM_DEVICE_INST, 0x0004)
+#define TI81XX_PRM_DEVICE_RSTST_OFFSET 0x0008
+#define TI81XX_PRM_DEVICE_RSTST TI81XX_PRCM_REGADDR(TI81XX_PRM_DEVICE_INST, 0x0008)
+
+/* CM_DEVICE */
+#define TI81XX_CM_DEVICE_CLKOUT_CTRL_OFFSET 0x0000
+#define TI81XX_CM_DEVICE_CLKOUT_CTRL TI81XX_PRCM_REGADDR(TI81XX_CM_DEVICE_INST, 0x0000)
+
+/* OCP_SOCKET_PRM */
+#define TI81XX_PRM_OCP_SOCKET_REVISION_OFFSET 0x0000
+#define TI81XX_PRM_OCP_SOCKET_REVISION TI81XX_PRCM_REGADDR(TI81XX_PRM_OCP_SOCKET_INST, 0x0000)
+
+/* CM_ACTIVE */
+#define TI81XX_CM_ACTIVE_GEM_CLKSTCTRL_OFFSET 0x0000
+#define TI81XX_CM_ACTIVE_GEM_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ACTIVE_INST, 0x0000)
+#define TI81XX_CM_ACTIVE_GEM_CLKCTRL_OFFSET 0x0020
+#define TI81XX_CM_ACTIVE_GEM_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ACTIVE_INST, 0x0020)
+
+/* CM_SGX */
+#define TI81XX_CM_SGX_SGX_CLKSTCTRL_OFFSET 0x0000
+#define TI81XX_CM_SGX_SGX_CLKSTCTRL TI81XX_PRCM_REGADDR(TI81XX_CM_SGX_INST, 0x0000)
+#define TI81XX_CM_SGX_SGX_SGX_CLKCTRL_OFFSET 0x0020
+#define TI81XX_CM_SGX_SGX_SGX_CLKCTRL TI81XX_PRCM_REGADDR(TI81XX_CM_SGX_INST, 0x0020)
+
+/* PRM_ACTIVE */
+#define TI81XX_PRM_ACTIVE_PM_PWRSTCTRL_OFFSET 0x0000
+#define TI81XX_PRM_ACTIVE_PM_PWRSTCTRL TI81XX_PRCM_REGADDR(TI81XX_PRM_ACTIVE_INST, 0x0000)
+#define TI81XX_PRM_ACTIVE_PM_PWRSTST_OFFSET 0x0004
+#define TI81XX_PRM_ACTIVE_PM_PWRSTST TI81XX_PRCM_REGADDR(TI81XX_PRM_ACTIVE_INST, 0x0004)
+#define TI81XX_PRM_ACTIVE_RM_RSTCTRL_OFFSET 0x0010
+#define TI81XX_PRM_ACTIVE_RM_RSTCTRL TI81XX_PRCM_REGADDR(TI81XX_PRM_ACTIVE_INST, 0x0010)
+#define TI81XX_PRM_ACTIVE_RM_RSTST_OFFSET 0x0014
+#define TI81XX_PRM_ACTIVE_RM_RSTST TI81XX_PRCM_REGADDR(TI81XX_PRM_ACTIVE_INST, 0x0014)
+
+/* PRM_SGX */
+#define TI81XX_PRM_SGX_PM_PWRSTCTRL_OFFSET 0x0000
+#define TI81XX_PRM_SGX_PM_PWRSTCTRL TI81XX_PRCM_REGADDR(TI81XX_PRM_SGX_INST, 0x0000)
+#define TI81XX_PRM_SGX_PM_PWRSTST_OFFSET 0x0004
+#define TI81XX_PRM_SGX_PM_PWRSTST TI81XX_PRCM_REGADDR(TI81XX_PRM_SGX_INST, 0x0004)
+#define TI81XX_PRM_SGX_RM_RSTCTRL_OFFSET 0x0010
+#define TI81XX_PRM_SGX_RM_RSTCTRL TI81XX_PRCM_REGADDR(TI81XX_PRM_SGX_INST, 0x0010)
+#define TI81XX_PRM_SGX_RM_RSTST_OFFSET 0x0014
+#define TI81XX_PRM_SGX_RM_RSTST TI81XX_PRCM_REGADDR(TI81XX_PRM_SGX_INST, 0x0014)
+
+/* CM_ALWON */
+#define TI81XX_CM_ALWON_L3_SLOW_CLKSTCTRL_OFFSET 0x0000
+#define TI81XX_CM_ALWON_L3_SLOW_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0000)
+#define TI81XX_CM_ETHERNET_CLKSTCTRL_OFFSET 0x0004
+#define TI81XX_CM_ETHERNET_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0004)
+#define TI81XX_CM_ALWON_L3_MED_CLKSTCTRL_OFFSET 0x0008
+#define TI81XX_CM_ALWON_L3_MED_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0008)
+#define TI81XX_CM_MMU_CLKSTCTRL_OFFSET 0x000C
+#define TI81XX_CM_MMU_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x000C)
+#define TI81XX_CM_MMUCFG_CLKSTCTRL_OFFSET 0x0010
+#define TI81XX_CM_MMUCFG_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0010)
+#define TI81XX_CM_ALWON_OCMC_0_CLKSTCTRL_OFFSET 0x0014
+#define TI81XX_CM_ALWON_OCMC_0_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0014)
+#define TI81XX_CM_ALWON_SYSCLK4_CLKSTCTRL_OFFSET 0x0020
+#define TI81XX_CM_ALWON_SYSCLK4_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0020)
+#define TI81XX_CM_ALWON_SYSCLK5_CLKSTCTRL_OFFSET 0x0024
+#define TI81XX_CM_ALWON_SYSCLK5_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0024)
+#define TI81XX_CM_ALWON_SYSCLK6_CLKSTCTRL_OFFSET 0x0028
+#define TI81XX_CM_ALWON_SYSCLK6_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0028)
+#define TI81XX_CM_ALWON_RTC_CLKSTCTRL_OFFSET 0x002C
+#define TI81XX_CM_ALWON_RTC_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x002C)
+#define TI81XX_CM_ALWON_L3_FAST_CLKSTCTRL_OFFSET 0x0030
+#define TI81XX_CM_ALWON_L3_FAST_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0030)
+#define TI81XX_CM_ALWON_MCASP0_CLKCTRL_OFFSET 0x0140
+#define TI81XX_CM_ALWON_MCASP0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0140)
+#define TI81XX_CM_ALWON_MCASP1_CLKCTRL_OFFSET 0x0144
+#define TI81XX_CM_ALWON_MCASP1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0144)
+#define TI81XX_CM_ALWON_MCASP2_CLKCTRL_OFFSET 0x0148
+#define TI81XX_CM_ALWON_MCASP2_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0148)
+#define TI81XX_CM_ALWON_MCBSP_CLKCTRL_OFFSET 0x014C
+#define TI81XX_CM_ALWON_MCBSP_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x014C)
+#define TI81XX_CM_ALWON_UART_0_CLKCTRL_OFFSET 0x0150
+#define TI81XX_CM_ALWON_UART_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0150)
+#define TI81XX_CM_ALWON_UART_1_CLKCTRL_OFFSET 0x0154
+#define TI81XX_CM_ALWON_UART_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0154)
+#define TI81XX_CM_ALWON_UART_2_CLKCTRL_OFFSET 0x0158
+#define TI81XX_CM_ALWON_UART_2_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0158)
+#define TI81XX_CM_ALWON_GPIO_0_CLKCTRL_OFFSET 0x015C
+#define TI81XX_CM_ALWON_GPIO_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x015C)
+#define TI81XX_CM_ALWON_GPIO_1_CLKCTRL_OFFSET 0x0160
+#define TI81XX_CM_ALWON_GPIO_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0160)
+#define TI81XX_CM_ALWON_I2C_0_CLKCTRL_OFFSET 0x0164
+#define TI81XX_CM_ALWON_I2C_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0164)
+#define TI81XX_CM_ALWON_I2C_1_CLKCTRL_OFFSET 0x0168
+#define TI81XX_CM_ALWON_I2C_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0168)
+#define TI81XX_CM_ALWON_TIMER_4_CLKCTRL_OFFSET 0x017C
+#define TI81XX_CM_ALWON_TIMER_4_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x017C)
+#define TI81XX_CM_ALWON_WDTIMER_CLKCTRL_OFFSET 0x018C
+#define TI81XX_CM_ALWON_WDTIMER_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x018C)
+#define TI81XX_CM_ALWON_SPI_CLKCTRL_OFFSET 0x0190
+#define TI81XX_CM_ALWON_SPI_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0190)
+#define TI81XX_CM_ALWON_MAILBOX_CLKCTRL_OFFSET 0x0194
+#define TI81XX_CM_ALWON_MAILBOX_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0194)
+#define TI81XX_CM_ALWON_SPINBOX_CLKCTRL_OFFSET 0x0198
+#define TI81XX_CM_ALWON_SPINBOX_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0198)
+#define TI81XX_CM_ALWON_MMUDATA_CLKCTRL_OFFSET 0x019C
+#define TI81XX_CM_ALWON_MMUDATA_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x019C)
+#define TI81XX_CM_ALWON_VLYNQ_CLKCTRL_OFFSET 0x01A0
+#define TI81XX_CM_ALWON_VLYNQ_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01A0)
+#define TI81XX_CM_ALWON_MMUCFG_CLKCTRL_OFFSET 0x01A8
+#define TI81XX_CM_ALWON_MMUCFG_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01A8)
+#define TI81XX_CM_ALWON_SDIO_CLKCTRL_OFFSET 0x01B0
+#define TI81XX_CM_ALWON_SDIO_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01B0)
+#define TI81XX_CM_ALWON_OCMC_0_CLKCTRL_OFFSET 0x01B4
+#define TI81XX_CM_ALWON_OCMC_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01B4)
+#define TI81XX_CM_ALWON_CONTROL_CLKCTRL_OFFSET 0x01C4
+#define TI81XX_CM_ALWON_CONTROL_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01C4)
+#define TI81XX_CM_ALWON_GPMC_CLKCTRL_OFFSET 0x01D0
+#define TI81XX_CM_ALWON_GPMC_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01D0)
+#define TI81XX_CM_ALWON_ETHERNET_0_CLKCTRL_OFFSET 0x01D4
+#define TI81XX_CM_ALWON_ETHERNET_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01D4)
+#define TI81XX_CM_ALWON_ETHERNET_1_CLKCTRL_OFFSET 0x01D8
+#define TI81XX_CM_ALWON_ETHERNET_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01D8)
+#define TI81XX_CM_ALWON_MPU_CLKCTRL_OFFSET 0x01DC
+#define TI81XX_CM_ALWON_MPU_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01DC)
+#define TI81XX_CM_ALWON_DEBUGSS_CLKCTRL_OFFSET 0x01E0
+#define TI81XX_CM_ALWON_DEBUGSS_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01E0)
+#define TI81XX_CM_ALWON_L3_CLKCTRL_OFFSET 0x01E4
+#define TI81XX_CM_ALWON_L3_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01E4)
+#define TI81XX_CM_ALWON_L4HS_CLKCTRL_OFFSET 0x01E8
+#define TI81XX_CM_ALWON_L4HS_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01E8)
+#define TI81XX_CM_ALWON_L4LS_CLKCTRL_OFFSET 0x01EC
+#define TI81XX_CM_ALWON_L4LS_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01EC)
+#define TI81XX_CM_ALWON_RTC_CLKCTRL_OFFSET 0x01F0
+#define TI81XX_CM_ALWON_RTC_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01F0)
+#define TI81XX_CM_ALWON_TPCC_CLKCTRL_OFFSET 0x01F4
+#define TI81XX_CM_ALWON_TPCC_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01F4)
+#define TI81XX_CM_ALWON_TPTC0_CLKCTRL_OFFSET 0x01F8
+#define TI81XX_CM_ALWON_TPTC0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01F8)
+#define TI81XX_CM_ALWON_TPTC1_CLKCTRL_OFFSET 0x01FC
+#define TI81XX_CM_ALWON_TPTC1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01FC)
+#define TI81XX_CM_ALWON_TPTC2_CLKCTRL_OFFSET 0x0200
+#define TI81XX_CM_ALWON_TPTC2_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0200)
+#define TI81XX_CM_ALWON_TPTC3_CLKCTRL_OFFSET 0x0204
+#define TI81XX_CM_ALWON_TPTC3_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0204)
+#define TI81XX_CM_ALWON_SR_0_CLKCTRL_OFFSET 0x0208
+#define TI81XX_CM_ALWON_SR_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0208)
+#define TI81XX_CM_ALWON_SR_1_CLKCTRL_OFFSET 0x020C
+#define TI81XX_CM_ALWON_SR_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x020C)
+
+/* Function prototypes */
+
+#endif
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