[PATCH 1/2] ARM: perf: reset counters on all CPUs during initialisation

[Jean Pihet]

Hi Will,

On Wed, Mar 23, 2011 at 2:39 PM, Will Deacon <will.deacon at arm.com> wrote:
> Hi Jean,
>
>> On Wed, Mar 16, 2011 at 4:38 PM, Will Deacon <will.deacon at arm.com> wrote:
>> > ARMv7 dictates that the interrupt-enable and count-enable registers for
>> > each PMU counter are UNKNOWN following core reset.
>> Great! Is this development driven by actual issues or by precaution?
>>
>> >
>> > This patch adds an arch_initcall to the ARMv7 perf events backend which
>> > disables the counters on each CPU prior to setting the Enable bit in the
>> > PMCR.
>> Also the function rename is a good thing.
>>
>> >
>> > Cc: Jean Pihet <jean.pihet at newoldbits.com>
>> > Signed-off-by: Will Deacon <will.deacon at arm.com>
>>
>> Acked-by: Jean Pihet <j-pihet at ti.com>
>
> I don't think this patch is safe for combined v6/v7 kernels because the
> arch_initcall will try to poke the v7 PMU regardless of whether or not
> it exists. I'll try and rework something and send another version to the
> list.
Ok. The new code should probably be called from *read_num_pmnc_events.

>
> I've removed it from the patch system but left the isb patch there
> because that is fine as it is.
Agree

>
> Stay tuned...
>
> Will
>
Thanks,
Jean

>
>
>
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